From patchwork Thu Jan 2 04:00:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yongqiang Niu X-Patchwork-Id: 206267 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9762EC2D0DD for ; Thu, 2 Jan 2020 04:02:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6ECA020863 for ; Thu, 2 Jan 2020 04:02:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="o3jzMvp8" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727715AbgABECb (ORCPT ); Wed, 1 Jan 2020 23:02:31 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:22585 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727686AbgABECb (ORCPT ); Wed, 1 Jan 2020 23:02:31 -0500 X-UUID: 1bd8b0d9da7748a3b90a729d83c0162f-20200102 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=IiiRHn3R6Js4Pvfh8uoHNNErfFDcDFJoVtSH9d23T4Y=; b=o3jzMvp86ezHPjkQT3ialNLQ97VPsiPiGH0a/i0i+UFjUEZd+NyKhMgtzz23z01vGKyRx/k3g+XCkSULEVlha/a06SdzAegmxxQgKW894G6dEXzgPDvqgy2oQ6JXu4ysG6Bbq8OGP5G7HSRO9XALRHjc0WBhLgKk5Yb1fNQcOnk=; X-UUID: 1bd8b0d9da7748a3b90a729d83c0162f-20200102 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 490112433; Thu, 02 Jan 2020 12:02:22 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 2 Jan 2020 12:01:56 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 2 Jan 2020 12:01:40 +0800 From: Yongqiang Niu To: CK Hu , Philipp Zabel , Rob Herring , Matthias Brugger CC: David Airlie , Daniel Vetter , Mark Rutland , , , , , , Yongqiang Niu Subject: [PATCH v6, 09/14] drm/mediatek: add connection from OVL_2L0 to RDMA0 Date: Thu, 2 Jan 2020 12:00:19 +0800 Message-ID: <1577937624-14313-10-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1577937624-14313-1-git-send-email-yongqiang.niu@mediatek.com> References: <1577937624-14313-1-git-send-email-yongqiang.niu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org this patch add add connection from OVL_2L0 to RDMA0 Signed-off-by: Yongqiang Niu Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -- 1.8.1.1.dirty diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index bb41594..a6fed7b 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -33,6 +33,12 @@ #define DISP_REG_CONFIG_DSI_SEL 0x050 #define DISP_REG_CONFIG_DPI_SEL 0x064 +#define MT8183_DISP_OVL0_2L_MOUT_EN 0xf04 +#define MT8183_DISP_PATH0_SEL_IN 0xf24 + +#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0) +#define DISP_PATH0_SEL_IN_OVL0_2L 0x1 + #define MT2701_DISP_MUTEX0_MOD0 0x2c #define MT2701_DISP_MUTEX0_SOF0 0x30 @@ -308,6 +314,10 @@ static unsigned int mtk_ddp_mout_en(const struct mtk_mmsys_reg_data *data, } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0) { *addr = data->ovl0_mout_en; value = OVL0_MOUT_EN_OVL0_2L; + } else if (cur == DDP_COMPONENT_OVL_2L0 && + next == DDP_COMPONENT_RDMA0) { + *addr = MT8183_DISP_OVL0_2L_MOUT_EN; + value = OVL0_2L_MOUT_EN_DISP_PATH0; } else { value = 0; } @@ -373,6 +383,10 @@ static unsigned int mtk_ddp_sel_in(const struct mtk_mmsys_reg_data *data, } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { *addr = DISP_REG_CONFIG_DPI_SEL; value = DPI_SEL_IN_BLS; + } else if (cur == DDP_COMPONENT_OVL_2L0 && + next == DDP_COMPONENT_RDMA0) { + *addr = MT8183_DISP_PATH0_SEL_IN; + value = DISP_PATH0_SEL_IN_OVL0_2L; } else { value = 0; }