From patchwork Thu Apr 25 10:41:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 162842 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1763404jan; Thu, 25 Apr 2019 03:41:01 -0700 (PDT) X-Google-Smtp-Source: APXvYqzxJKoh+jC63B+MUpEPVu1msRiklCGy94QgCsm1RbCehcdQLOvhZGkpsBgfaTD0pGC4/C/g X-Received: by 2002:a65:44c6:: with SMTP id g6mr35752499pgs.157.1556188860978; Thu, 25 Apr 2019 03:41:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556188860; cv=none; d=google.com; s=arc-20160816; b=IlE+D7ivTc6fY3HLPbsdFN+lIL7eWQO2WY59Ts/KO9XVMvczXzxJNCMLFb/Zt1NO7m SPQzm8RtQww2aRZ8PahcOBcQ4iJw+NbyTyJFB+340wQ+Qa1PbeYQJd1uwgIvnPUShsz6 s2/vAZl2ltgjXQWS7CmypeViBpmKyywFmBbeWJWfqXhCjyXMR/yONkTAEMD7IBvxmPsK b7OIUAygc5u6MTzoEwqqGGsHP/op/wofPh9iNeNQzwF+MMCzoGbgLp50UP5gDsNLbwLO jhR9vwKOBKkdc5eRsT/DMcZIeCZkp47SqeO3VswO/sAinObzRagzOhxUnPIuuikBckj8 wCrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=7jDX1NX2/EG6DguwQ8zIYKVZRY2pkw753IO6TmO/ZBE=; b=tujP4KFWaXwYhOXTLyMoeCcscj6mEwZLGKFf7NtmDEoqeaoSWF/wcTn4tydYZ7AoET Ln/S8X6JygneozzcX5mLkGq1WPJume/GwZm0oy44EbLuSVJvMzhcKfYVTV6jjHXIDwEM ameUtA8oFEktQlJwxfueV02O3YyYijR1hKzJMtuMUNgsABFpFU4oTu2jVxHdxf/bzW42 2UvKScjF7SIfQ5KZPpNc7kDHlfsrQuR+xf26yeOxgrppUf8kD8uBUpKjCqOKoXT7i0RV Pif01oX+DiQKKgYBGFSgY/Id8/HifOQKD5xqs9xgBLn3IwSt57PuhO1Og43RT6lw/eyw 78CA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ba5si21232147plb.24.2019.04.25.03.41.00; Thu, 25 Apr 2019 03:41:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730436AbfDYKk6 (ORCPT + 7 others); Thu, 25 Apr 2019 06:40:58 -0400 Received: from mx.socionext.com ([202.248.49.38]:5348 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730396AbfDYKk6 (ORCPT ); Thu, 25 Apr 2019 06:40:58 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 25 Apr 2019 19:40:56 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 0E2FE180C0C; Thu, 25 Apr 2019 19:40:56 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Thu, 25 Apr 2019 19:40:56 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by kinkan.css.socionext.com (Postfix) with ESMTP id 93A4F1A04E0; Thu, 25 Apr 2019 19:40:55 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 74147121BD0; Thu, 25 Apr 2019 19:40:55 +0900 (JST) From: Sugaya Taichi To: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland Cc: Takao Orito , Kazuhiro Kasai , Shinji Kanematsu , Jassi Brar , Masami Hiramatsu , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Sugaya Taichi Subject: [PATCH v3 1/3] dt-bindings: clock: milbeaut: add Milbeaut clock description Date: Thu, 25 Apr 2019 19:41:00 +0900 Message-Id: <1556188862-22546-2-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1556188862-22546-1-git-send-email-sugaya.taichi@socionext.com> References: <1556188862-22546-1-git-send-email-sugaya.taichi@socionext.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT bindings document for Milbeaut clock. Signed-off-by: Sugaya Taichi --- .../devicetree/bindings/clock/milbeaut-clock.yaml | 73 ++++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/milbeaut-clock.yaml -- 1.9.1 diff --git a/Documentation/devicetree/bindings/clock/milbeaut-clock.yaml b/Documentation/devicetree/bindings/clock/milbeaut-clock.yaml new file mode 100644 index 0000000..5cf0b81 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/milbeaut-clock.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/clock/milbeaut-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Milbeaut SoCs Clock Controller Binding + +maintainers: + - Taichi Sugaya + +description: | + Milbeaut SoCs Clock controller is an integrated clock controller, which + generates and supplies to all modules. + + This binding uses common clock bindings + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +properties: + compatible: + oneOf: + - items: + - enum: + - socionext,milbeaut-m10v-ccu + clocks: + maxItems: 1 + description: external clock + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +examples: + # Clock controller node: + - | + m10v-clk-ctrl@1d021000 { + compatible = "socionext,milbeaut-m10v-clk-ccu"; + reg = <0x1d021000 0x4000>; + #clock-cells = <1>; + clocks = <&clki40mhz>; + }; + + # Required an external clock for Clock controller node: + - | + clocks { + clki40mhz: clki40mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + }; + /* other clocks */ + }; + + # The clock consumer shall specify the desired clock-output of the clock + # controller as below by specifying output-id in its "clk" phandle cell. + # 2: uart + # 4: 32-bit timer + # 7: UHS-I/II + - | + serial@1e700010 { + compatible = "socionext,milbeaut-usio-uart"; + reg = <0x1e700010 0x10>; + interrupts = <0 141 0x4>, <0 149 0x4>; + interrupt-names = "rx", "tx"; + clocks = <&clk 2>; + }; + +...