From patchwork Fri Aug 31 15:14:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 145684 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp901546ljw; Fri, 31 Aug 2018 08:15:35 -0700 (PDT) X-Google-Smtp-Source: ANB0Vdba8Z78U1uJVuD/fgrtq9BUKTfw7wsQmmZBbz+ef1GdjvGL3GPp2ZOexy5pNeQWeQ4dahZ9 X-Received: by 2002:a17:902:7683:: with SMTP id m3-v6mr16170101pll.255.1535728535031; Fri, 31 Aug 2018 08:15:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535728535; cv=none; d=google.com; s=arc-20160816; b=ikia9UruJVOlNcnrG5gwRpGxVmVlUNnXy4a9/OsagDJC0OME/5XbpLG3NYsC+QV1Ds bY3rBOiQvP8vn5pFKbFd9k1omMUpB65t2Yx9+R0V2EIyXFOk/isSiVlnVG2M14jeXBGn mnAbTxUMG+k7r26x/+4ltDawOHiF7mHjtxavX+nacNqGT3iTneMjChmGZA9DX/tKbqqV WLygOMjeF9g4wlBG4/sE6olKO3Kja9X4ktAiaCgPzDV/8b/N5eusy2diRUXgoN6pvpuH Ya0oIoI6Wmdou09MNeA2+zdxKmbXLcaYSmPiQsnXiPBCQoOul3qhsA82aYG0LPOGHkq+ Mqog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=tQG56QjJ21xIAGgnUHPtl/XLIyR7xUyJCLC8//WE1VE=; b=f54CiHNwZZY/hphq48FYmStgCLYKhxijiSiGCupHs1Zo+kWJ8hX3NweJHdQiMPr0pb PitrWE6OakJOQKxZBDGspWq0Y5ktbVQ1gFBUZ5HWkIZY5YuTHQyeXpG9+vt+XWsu085s VwNjLycs9rVFUVrHseDDZi8OYaQQrGbgPX0I0YSMH3hfkasJyC3ipeduhCZKwp/mKMZe 1vbJo8GTOep9CYc96WL8dzwO/Y56NoL87GwW9q1+kcVt0bvV3Hb7qY/TYLEgEkGuI+Fq j3hbtAcrxRjwMtY2IE04MjI8rIKox8RgLM+B/CUZMzhWWT4L7dgl6A737jgjUJdLOIcU 2QKA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=wUORooAq; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n3-v6si10359269pld.146.2018.08.31.08.15.34; Fri, 31 Aug 2018 08:15:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=wUORooAq; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728032AbeHaTXb (ORCPT + 6 others); Fri, 31 Aug 2018 15:23:31 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:35608 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727303AbeHaTXa (ORCPT ); Fri, 31 Aug 2018 15:23:30 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id w7VFFCH2021651; Fri, 31 Aug 2018 10:15:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1535728512; bh=tQG56QjJ21xIAGgnUHPtl/XLIyR7xUyJCLC8//WE1VE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=wUORooAqpGfR60P3XESkvi/ssYZH+rlOkJem8vKn/pqSXDzuZELC7i3oykZFhgEJ1 kxwtq951SZqiARz8qZbb26T21iNtp3Jv/cgGWM7AxoNfb6KCfZ0/O9tL8Xxb+OZJLB FBQ1okFZTAN1geQVjtEzGEKMrWp0hri8/PbShaVE= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w7VFFCWM014239; Fri, 31 Aug 2018 10:15:12 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 31 Aug 2018 10:15:12 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 31 Aug 2018 10:15:12 -0500 Received: from gomoku.home (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w7VFF7G3022474; Fri, 31 Aug 2018 10:15:11 -0500 From: Tero Kristo To: , CC: Subject: [PATCH 2/3] ARM: dts: am43xx: convert to use new clkctrl layout Date: Fri, 31 Aug 2018 18:14:50 +0300 Message-ID: <1535728491-25321-3-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1535728491-25321-1-git-send-email-t-kristo@ti.com> References: <1535728491-25321-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert AM43xx to use the new clockdomain based layout. Previously the clkctrl split was based on CM isntance boundaries. The new layout helps with introducing the interconnect driver instances. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/am4372.dtsi | 4 +- arch/arm/boot/dts/am43xx-clocks.dtsi | 74 ++++++++++++++++++++++++++++++------ 2 files changed, 64 insertions(+), 14 deletions(-) -- 1.9.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index f0cbd86..7fafbea 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -1016,7 +1016,7 @@ reg = <0x483a8000 0x8000>; syscon-phy-power = <&scm_conf 0x620>; clocks = <&usb_phy0_always_on_clk32k>, - <&l4_per_clkctrl AM4_USB_OTG_SS0_CLKCTRL 8>; + <&l3s_clkctrl AM4_L3S_USB_OTG_SS0_CLKCTRL 8>; clock-names = "wkupclk", "refclk"; #phy-cells = <0>; status = "disabled"; @@ -1035,7 +1035,7 @@ reg = <0x483e8000 0x8000>; syscon-phy-power = <&scm_conf 0x628>; clocks = <&usb_phy1_always_on_clk32k>, - <&l4_per_clkctrl AM4_USB_OTG_SS1_CLKCTRL 8>; + <&l3s_clkctrl AM4_L3S_USB_OTG_SS1_CLKCTRL 8>; clock-names = "wkupclk", "refclk"; #phy-cells = <0>; status = "disabled"; diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index a7037a4..e3f4207 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -710,73 +710,123 @@ }; &prcm { - l4_wkup_cm: l4_wkup_cm@2800 { + wkup_cm: wkup-cm@2800 { compatible = "ti,omap4-cm"; reg = <0x2800 0x400>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x2800 0x400>; - l4_wkup_clkctrl: clk@20 { + l3s_tsc_clkctrl: l3s-tsc-clkctrl@120 { compatible = "ti,clkctrl"; - reg = <0x20 0x34c>; + reg = <0x120 0x4>; #clock-cells = <2>; }; + + l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@228 { + compatible = "ti,clkctrl"; + reg = <0x228 0xc>; + #clock-cells = <2>; + }; + + l4_wkup_clkctrl: l4-wkup-clkctrl@220 { + compatible = "ti,clkctrl"; + reg = <0x220 0x4>, <0x328 0x44>; + #clock-cells = <2>; + }; + }; - mpu_cm: mpu_cm@8300 { + mpu_cm: mpu-cm@8300 { compatible = "ti,omap4-cm"; reg = <0x8300 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x8300 0x100>; - mpu_clkctrl: clk@20 { + mpu_clkctrl: mpu-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - gfx_l3_cm: gfx_l3_cm@8400 { + gfx_l3_cm: gfx-l3-cm@8400 { compatible = "ti,omap4-cm"; reg = <0x8400 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x8400 0x100>; - gfx_l3_clkctrl: clk@20 { + gfx_l3_clkctrl: gfx-l3-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - l4_rtc_cm: l4_rtc_cm@8500 { + l4_rtc_cm: l4-rtc-cm@8500 { compatible = "ti,omap4-cm"; reg = <0x8500 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x8500 0x100>; - l4_rtc_clkctrl: clk@20 { + l4_rtc_clkctrl: l4-rtc-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - l4_per_cm: l4_per_cm@8800 { + per_cm: per-cm@8800 { compatible = "ti,omap4-cm"; reg = <0x8800 0xc00>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x8800 0xc00>; - l4_per_clkctrl: clk@20 { + l3_clkctrl: l3-clkctrl@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x3c>, <0x78 0x2c>; + #clock-cells = <2>; + }; + + l3s_clkctrl: l3s-clkctrl@68 { + compatible = "ti,clkctrl"; + reg = <0x68 0xc>, <0x220 0x4c>; + #clock-cells = <2>; + }; + + pruss_ocp_clkctrl: pruss-ocp-clkctrl@320 { compatible = "ti,clkctrl"; - reg = <0x20 0xb04>; + reg = <0x320 0x4>; #clock-cells = <2>; }; + + l4ls_clkctrl: l4ls-clkctrl@420 { + compatible = "ti,clkctrl"; + reg = <0x420 0x1a4>; + #clock-cells = <2>; + }; + + emif_clkctrl: emif-clkctrl@720 { + compatible = "ti,clkctrl"; + reg = <0x720 0x4>; + #clock-cells = <2>; + }; + + dss_clkctrl: dss-clkctrl@a20 { + compatible = "ti,clkctrl"; + reg = <0xa20 0x4>; + #clock-cells = <2>; + }; + + cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@b20 { + compatible = "ti,clkctrl"; + reg = <0xb20 0x4>; + #clock-cells = <2>; + }; + }; };