From patchwork Fri Jul 20 08:50:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 142462 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp2699720ljj; Fri, 20 Jul 2018 01:51:48 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfSvUG5D7/ncvBkZ7TefygT6AUGYn412+zaEdSCrzBkz1sruGYwVCT9rOcuPpovgk20Nt2l X-Received: by 2002:a65:5803:: with SMTP id g3-v6mr1217978pgr.117.1532076708367; Fri, 20 Jul 2018 01:51:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532076708; cv=none; d=google.com; s=arc-20160816; b=DENofhZWjfIFFA/Z5yZoHDzVGFBgdHTSZwYtZuWvIQB7U6GICMCgQ8TZMj2mfWYn4r WJJNaU5k7/sL98HkvaFp8ioXed43+o7QJf3X4AMH1jqg3+y+0JhrqjJ+nvzWytMyhGiZ g9ZD3qKQD/IX1Tfm0Mi0KYzKFk6nhIzskBkTcZvlDnGEeWEPgLzo3QNot2WmjeGlzi1B h6mugm1zeVXuPZw7TGYeG41mIfkvC0vlInFOs3PoAlLrLyXNMVvS1zj0pdDP1kPuewfG /o/b40NFmdqo5mdDMppxEVpzRDgD/pAV68r5a++B2Sjh8RW9Kg6gqM9I4xHErvCFPSEv yeTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=wgANsywr6aiDpGQ5Qxt3FMDhJ9tYZ6zktiIOQCz/6Vo=; b=EOTsabmRId21nnzTh3S4U4dRR8wiOtwfAejGxWo0XRNZBTZMn99LjFnXtvL4L8ZO68 VEalxE95+noosUFORnRhAFzEGH0X2IVV4eVIrA74sf4PNobDZlOFY7qwywq45qnSt3ZL +u6FQPCl+2rGv24qAA/xqe+c0zCmtBneorYhp+RX6h5cfSg/IiLr618k9BHZKSm8Da/e 26qLSRJTZQLXJatUB//J6ATC9gFBZc5UJ1dlKtFJt2L8EAcg3jWm8obnysxc0hF9vzj9 thSLm81ha80zOTPTUbyP6aBMg9Iaf962QFV8+KPoNEnzvojyIAy7+MHw9MAZ416bpr+O ONUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=bjQU0+ao; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o1-v6si1288946pge.572.2018.07.20.01.51.48; Fri, 20 Jul 2018 01:51:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=bjQU0+ao; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727216AbeGTJjB (ORCPT + 5 others); Fri, 20 Jul 2018 05:39:01 -0400 Received: from conuserg-07.nifty.com ([210.131.2.74]:40368 "EHLO conuserg-07.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727056AbeGTJjA (ORCPT ); Fri, 20 Jul 2018 05:39:00 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-07.nifty.com with ESMTP id w6K8ovEI003659; Fri, 20 Jul 2018 17:50:59 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com w6K8ovEI003659 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1532076659; bh=+GnWeTGMhTuXzAahaXcxKYC72mrpNXaL4W1DzGd3qOo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bjQU0+aooD4IHGIlRXas7ec/LQr5T9rQ8t2W9M8oMTkvqvbHhFQAW60v3s/JNipHI Pi0B27dCD8Tn89ZxOW7vdHRd9TeqoRBIKbrZ7TwwTAbu7+QRkVlLLzsKvIdGhGoOWC PlJ7cOuEhJzyUVL7puhP6gF62k9UF4UKfr5jOS0DeprNJsWgqkdRcH+ZOnhma38Hi4 hYBY0YasECxLHsqu5TTNN1f8jTNI4SRicX62m5JbQVGydcym39Hl86Ph0K855NA/OE fmttW6NUkZhX4i2R/2hekiCF4rQe1mnX1FVYCkmdgqzJ3J1p66+Dg8Kvh7atvzIU2F Oa65AsfHHJFdA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-arm-kernel@lists.infradead.org Cc: Boris Brezillon , Rob Herring , Masami Hiramatsu , Jassi Brar , Masahiro Yamada , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Will Deacon , Mark Rutland , Catalin Marinas Subject: [PATCH 2/2] arm64: uniphier: dts: add more clocks to Denali NAND controller node Date: Fri, 20 Jul 2018 17:50:45 +0900 Message-Id: <1532076645-10769-2-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532076645-10769-1-git-send-email-yamada.masahiro@socionext.com> References: <1532076645-10769-1-git-send-email-yamada.masahiro@socionext.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Catch up with the new binding of the Denali IP where three clocks, "nand", "nand_x", "ecc" are required. For UniPhier SoCs, the "nand_x" and "ecc" are tied up because they are both 200MHz. Signed-off-by: Masahiro Yamada --- arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 3 ++- arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 3 ++- arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi index d63b56e..5640dac 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -571,7 +571,8 @@ interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; - clocks = <&sys_clk 2>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; }; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index 0298bd0..a8964c0 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -626,7 +626,8 @@ interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; - clocks = <&sys_clk 2>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; }; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi index 2a4cf42..fd2bcd4 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi @@ -455,7 +455,8 @@ interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; - clocks = <&sys_clk 2>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; }; };