From patchwork Fri Mar 2 01:12:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 130435 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp719878lja; Thu, 1 Mar 2018 17:12:46 -0800 (PST) X-Google-Smtp-Source: AG47ELtiDQ0qZ7uZz4cRHomY2k/RP/fIoRzOVUmyiGsPh54ORCFq0J+ihu26KtGlop98nDxz0qum X-Received: by 2002:a17:902:ba95:: with SMTP id k21-v6mr3697443pls.111.1519953166069; Thu, 01 Mar 2018 17:12:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519953166; cv=none; d=google.com; s=arc-20160816; b=viWrR4XCwD03ZpALySU8uGKvTVQMQn/03zsCMpcaaY/Zw4hsN7FrfDyJrKUwTKDsI1 VyWuZmrif3EaSsCHBAE0h24TgQVNT3xSCJ3v3MOgczRIbw2jLzB3Vrfh9p9WyH9GGjep 6BvK+84DTr1so0v0j0KwkIdyYXgWCr87Tvexnb1Z5m5WiMy6HtAyxaG3A6QJXG6mm7nO FsaPXD55mNwqyUptPGWtVNp5NrQCey/yCKH+kOOWBtL7rthj0AFBAan9jElaVbPF9nIQ 4BZgpgHhAyLOeAahJ7Xh3BkV9egEVD0wONbtIe8bJJvuR1V5xNwF4KRoVedFBZ474C9V PzoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=wK1Cia9UV8H7scSdo98ARxz78fHjlhdm2Y44mjrnwPc=; b=FSqZ9iremvW/R6CvcBgx/Dm0f/1oNufaHy6Jxr9YNEHmMwBd1vmq2RkZFziqRUJIVi WyR3/Re2D4t1J1Dxr+OF8WusvtUkQLGLvMLY/bpadErTI6T+xT6Yu7NcMxmHcyLmcUmQ spkp+Ph7L6dmkYcTTx7QQY5DSotlRZs7eHARFZxf3ICxz2QpaAGgg4cPc+hfknP/DZOe 3DaNgP/5V+qt3eWhlrMmXL405+SOk9nk2UsGQtaZA3hHlHoTVsgfbB4+7JRphwzbCiEJ Q4sTRLYslVOSHIRd1PXjeCKZhWURuQ7Pry5epl1W9gDcM3Wg/Xrl/lo3bVQgSqZw0nEf Vx7A== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=QgE5+yWK; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g1si3148030pge.831.2018.03.01.17.12.45; Thu, 01 Mar 2018 17:12:46 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=QgE5+yWK; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1163375AbeCBBMo (ORCPT + 6 others); Thu, 1 Mar 2018 20:12:44 -0500 Received: from mail-pl0-f66.google.com ([209.85.160.66]:41671 "EHLO mail-pl0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1163289AbeCBBMn (ORCPT ); Thu, 1 Mar 2018 20:12:43 -0500 Received: by mail-pl0-f66.google.com with SMTP id k8-v6so4697929pli.8 for ; Thu, 01 Mar 2018 17:12:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KNbIZ1J21VEN3dP21fHyUZ8Xc2OpfYBzPaI21LhPJIc=; b=QgE5+yWKcD+VeCmFvIb3S42BarMy+suB0KfMZans224gkGrO+UQfX0iez6nnWClJvQ ri5bje+dZnwpaLrtiNoXKWVZ4/rOEMNZoJD9Mqtq83rADMK0lblRQMnd+SLEMPwkhZFV Fxj2lrLNIaUlteDaCP6rIDZG0mvEm/mkzOhUQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KNbIZ1J21VEN3dP21fHyUZ8Xc2OpfYBzPaI21LhPJIc=; b=gjFcR1L8SlsoBblmdEWt68ib0yuMuZx2rfp7mfVw4mt4sF2RW/Tq25zTYTr1QaU5He p1hRiztbCYu9guVmKVJYtRL+zYUw2Fe+x3n62Q56g7j6iyOMSssC61kYucuzgL+0Zwyy iHzKWIfTaf0Qf7FDOftFW274M8XiOBkdnqQfi4Az5XGHctNd4cMcVaQAwmpbkALqBxgc BnGzqVnISatY9L9zyI3wtGfxf2Hqr2uWdr693bTWH9+u4C5BTTsXqT26oeKrOFng2pTd pWa0X0QKQXh2y8ctklCBe8dhNDLVoVcG/zmRnoJfeGc1iSGfxuwWrDZR64AMa3AFjl2Y DS8Q== X-Gm-Message-State: APf1xPBNN9Bt3/cCHpFeugDz4QkT3Ssstav+4OYFJYavyYwK2YAiKfF2 Rt3xv2+UfXGzWti7CpbxC76r+A== X-Received: by 2002:a17:902:8d93:: with SMTP id v19-v6mr3593821plo.371.1519953162756; Thu, 01 Mar 2018 17:12:42 -0800 (PST) Received: from localhost.localdomain ([45.56.152.106]) by smtp.gmail.com with ESMTPSA id z22sm2186864pfd.158.2018.03.01.17.12.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 01 Mar 2018 17:12:41 -0800 (PST) From: Shawn Guo To: Lorenzo Pieralisi Cc: Bjorn Helgaas , Rob Herring , Fabio Estevam , Jianguo Sun , Jiancheng Xue , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Shawn Guo Subject: [PATCH v3 2/2] PCI: histb: Add an optional regulator for PCIe port power control Date: Fri, 2 Mar 2018 09:12:01 +0800 Message-Id: <1519953121-28218-3-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1519953121-28218-1-git-send-email-shawn.guo@linaro.org> References: <1519953121-28218-1-git-send-email-shawn.guo@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The power supply to PCIe port are often controlled by GPIO on some board designs. Let's add an optional regulator which can be backed by GPIO to control the power. Signed-off-by: Shawn Guo Acked-by: Rob Herring --- .../bindings/pci/hisilicon-histb-pcie.txt | 1 + drivers/pci/dwc/pcie-histb.c | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt index c84bc027930b..760b4d740616 100644 --- a/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt +++ b/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt @@ -34,6 +34,7 @@ Required properties Optional properties: - reset-gpios: The gpio to generate PCIe PERST# assert and deassert signal. +- vpcie-supply: The regulator in charge of PCIe port power. - phys: List of phandle and phy mode specifier, should be 0. - phy-names: Must be "phy". diff --git a/drivers/pci/dwc/pcie-histb.c b/drivers/pci/dwc/pcie-histb.c index 17ed604f5741..4cef0a514944 100644 --- a/drivers/pci/dwc/pcie-histb.c +++ b/drivers/pci/dwc/pcie-histb.c @@ -61,6 +61,7 @@ struct histb_pcie { struct reset_control *bus_reset; void __iomem *ctrl; int reset_gpio; + struct regulator *vpcie; }; static u32 histb_pcie_readl(struct histb_pcie *histb_pcie, u32 reg) @@ -227,6 +228,9 @@ static void histb_pcie_host_disable(struct histb_pcie *hipcie) if (gpio_is_valid(hipcie->reset_gpio)) gpio_set_value_cansleep(hipcie->reset_gpio, 0); + + if (hipcie->vpcie) + regulator_disable(hipcie->vpcie); } static int histb_pcie_host_enable(struct pcie_port *pp) @@ -237,6 +241,14 @@ static int histb_pcie_host_enable(struct pcie_port *pp) int ret; /* power on PCIe device if have */ + if (hipcie->vpcie) { + ret = regulator_enable(hipcie->vpcie); + if (ret) { + dev_err(dev, "failed to enable regulator: %d\n", ret); + return ret; + } + } + if (gpio_is_valid(hipcie->reset_gpio)) gpio_set_value_cansleep(hipcie->reset_gpio, 1); @@ -282,6 +294,8 @@ static int histb_pcie_host_enable(struct pcie_port *pp) err_sys_clk: clk_disable_unprepare(hipcie->bus_clk); err_bus_clk: + if (hipcie->vpcie) + regulator_disable(hipcie->vpcie); return ret; } @@ -331,6 +345,13 @@ static int histb_pcie_probe(struct platform_device *pdev) return PTR_ERR(pci->dbi_base); } + hipcie->vpcie = devm_regulator_get_optional(dev, "vpcie"); + if (IS_ERR(hipcie->vpcie)) { + if (PTR_ERR(hipcie->vpcie) == -EPROBE_DEFER) + return -EPROBE_DEFER; + hipcie->vpcie = NULL; + } + hipcie->reset_gpio = of_get_named_gpio_flags(np, "reset-gpios", 0, &of_flags); if (of_flags & OF_GPIO_ACTIVE_LOW)