From patchwork Tue Dec 19 15:24:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Gerlach X-Patchwork-Id: 122387 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp4296622qgn; Tue, 19 Dec 2017 07:25:57 -0800 (PST) X-Google-Smtp-Source: ACJfBouzTgaShHmDaEwz+4/eh0AoOWhjD183hSkqDKQvjKL3D1EHwz9YPyZPiJbs2yA+ZmQkTSKT X-Received: by 10.101.77.133 with SMTP id p5mr3418694pgq.101.1513697157577; Tue, 19 Dec 2017 07:25:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513697157; cv=none; d=google.com; s=arc-20160816; b=a5HYp9Q/2BkkeXjAne2SVy2RrLxTaphobf7pzGk2mOUn37kwiJt1UOB1nZz2Aj3Sru YvfiZF860EBF4t3U6euMEOq5ytpsWz3h74pYzaguB9lw5GPV4ZW5TMXjukPh4iEPSaeb R5jL0fZ+fR1pU2rkATgYveVTEyWtQE1AmbUOLoJOk8mFEchSUf+UfbKAU+dmVoBEVrHK kuC7JzzQ3l6jwR8rFw054AoE4LI6QGFjFoSyJNEBcDeOJ5dFNZSTb4n9NllBZd1wf7mX Ka1jkeINpTePn0oaXbbdzLVB2ql2cL74hBvubwV6ngt1//eB/R5qEzTRvTsv729XKk8p Cc9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=eR7zZVyRXXxAS1g4qiQ8SOm8NpTc5nBySXZGsRd3HiQ=; b=TK+7VLYZL1vGpgQvYPlRPRHF1Xit7Km5l4qXuLYGe37YJRHv/MaZMDH25MJaWWei3W T7K9uIf8eeLw3P4aB1rL7hKJQTKoqDks1TFNeKqocoAYtRFdYG08C+JhIycG64e1LOaj w3Rti3H4U8CM+9L1NYA57hi/89E/VAD+vk3gWhZFFC99m34Ja0bKQMJ84DELfHjxQ+Jb z6U9MA7XJjt4u5pqdKvnV1aW13+z8mE5Tjy52u+NNnsgmDg502m8L12+DYjXSOWSDSxZ UdZIKIrME+vlPOfGPX7j0aiybvKtpf1ePixAMp/6PJ94i5L+3XtazlbAryVebYkvj1tA 0VNg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=DzMd+HiT; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b35si10730632plh.55.2017.12.19.07.25.57; Tue, 19 Dec 2017 07:25:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=DzMd+HiT; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751805AbdLSPZ4 (ORCPT + 6 others); Tue, 19 Dec 2017 10:25:56 -0500 Received: from fllnx210.ext.ti.com ([198.47.19.17]:47291 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752443AbdLSPZx (ORCPT ); Tue, 19 Dec 2017 10:25:53 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id vBJFPHKo023634; Tue, 19 Dec 2017 09:25:17 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1513697117; bh=p7S4BD9kkVFpNqbfhoRCZZ/BBStaIPA6fGUwXZX/85Y=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=DzMd+HiTvJU4rPNdcbMTOkgpJNkHofZZz6oOEZgYJt72e9Rhq+jUo1ao0nrsRs2Fa Upql1fdLyE0Uf0qNYxH3Vs8wWK5xH09aQxetlAyc0dSNCK/LLCxNzzmiyLU9byADBH O6/a0GxxBriRFZrMNEapJ34jfPq6FdQ23OUTPtjk= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBJFPHWr012650; Tue, 19 Dec 2017 09:25:17 -0600 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 19 Dec 2017 09:25:17 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 19 Dec 2017 09:25:17 -0600 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBJFPHod031941; Tue, 19 Dec 2017 09:25:17 -0600 Received: from localhost (uda0274052.dhcp.ti.com [128.247.59.203]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id vBJFPHx00857; Tue, 19 Dec 2017 09:25:17 -0600 (CST) From: Dave Gerlach To: Tony Lindgren CC: , , , Nishanth Menon , Dave Gerlach Subject: [PATCH 1/8] ARM: dts: dra7: Add vbb-supply to cpu and additional voltages Date: Tue, 19 Dec 2017 09:24:19 -0600 Message-ID: <1513697066-27732-2-git-send-email-d-gerlach@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1513697066-27732-1-git-send-email-d-gerlach@ti.com> References: <1513697066-27732-1-git-send-email-d-gerlach@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a vbb-supply phandle to the cpus node and also add an additional triplet of voltages for each OPP in the operating-points-v2 table to make use of the multi regulator support in the OPP core and provide the vbb regulator for use by the ti-opp-supply driver. Signed-off-by: Dave Gerlach --- arch/arm/boot/dts/dra7.dtsi | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) -- 2.15.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index ac9216293b7c..d9f60144793b 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -92,6 +92,8 @@ cooling-min-level = <0>; cooling-max-level = <2>; #cooling-cells = <2>; /* min followed by max */ + + vbb-supply = <&abb_mpu>; }; }; @@ -101,14 +103,17 @@ opp_nom-1000000000 { opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1060000 850000 1150000>; + opp-microvolt = <1060000 850000 1150000>, + <1060000 850000 1150000>; opp-supported-hw = <0xFF 0x01>; opp-suspend; }; opp_od-1176000000 { opp-hz = /bits/ 64 <1176000000>; - opp-microvolt = <1160000 885000 1160000>; + opp-microvolt = <1160000 885000 1160000>, + <1160000 885000 1160000>; + opp-supported-hw = <0xFF 0x02>; }; };