From patchwork Mon Dec 4 08:12:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Keiji Hayashibara X-Patchwork-Id: 120491 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp4137806qgn; Mon, 4 Dec 2017 00:12:55 -0800 (PST) X-Google-Smtp-Source: AGs4zMZ5MPy4N0GoDNw5udw53ecnDigSO3LeZkiJgHg7/QrO5Ir+PyjaOBbDkCC9xEDe+Eu7OcCx X-Received: by 10.159.196.151 with SMTP id c23mr1263049plo.1.1512375175517; Mon, 04 Dec 2017 00:12:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512375175; cv=none; d=google.com; s=arc-20160816; b=vSLazLs4kym8py4UkPRWH6dpCsaAr/jj7eJMty2qn/iMuOZ6jHm+VnZz4QOoCG2us5 9XiJnbfqIyM1/PITkmOAeXGSXmNu335Urv/GVJmBQT8K0T1djC0TKUD84ZCclSXPAWn7 X8ckyQxgg3C3quD9w1VE0icVuv9QvJD/K6cOvNXDaGGc3p1cOOECT5rAK5yvDrK0V41r y00LLKqfVA2AjSyMtTcXaTH59oqDBzKdqcy+ZCopwE0bo97zp7eMA5mUNDck7ErnX42e 6bmb/QKhDy0yFC1zNhwpUdujkuSFWPG0QarBuiDIJs949agFEQBM7ZQ+CxOjDFuTR6o3 XwPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :arc-authentication-results; bh=kjqayWeYaSEMqLmgj92deSwl5nEGg5ZuPc3Ffdpw29E=; b=TwciEhBVgyIFXt/PSsWKjZ7q4DfkpVnmmPIBTl/1uvQJqzyui5rDrlizJd0qulysrq fOAhAtYHgNe/4tEjhiqviIJGJGwbbcEYEIRQU6l+qBdG8gPWSbmVOWht09oSkFtFUHkB BMiCwGFHVniIn7+KE80Rt8K23WrY8cntPMZcArbGfHo9Apw7LN0RsVLYpWpZGsTz0sft pMzL9INAUSdKTB0P17K631uQ7lPnHsswRL880m22sZCP8BNSPFLHso+pOFRiY7t5Snxf YkEpq6aYheBsuyLcTrHM06SckfPnf74QSrCv49nqAR68r4a6KrpHEMtd8txsAOGaPd+W nkOA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p8si9066010pgn.723.2017.12.04.00.12.55; Mon, 04 Dec 2017 00:12:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752930AbdLDIMy (ORCPT + 6 others); Mon, 4 Dec 2017 03:12:54 -0500 Received: from mx.socionext.com ([202.248.49.38]:44752 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752823AbdLDIMx (ORCPT ); Mon, 4 Dec 2017 03:12:53 -0500 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 04 Dec 2017 17:12:52 +0900 Received: from mail.mfilter.local (unknown [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 80E5D180E8A; Mon, 4 Dec 2017 17:12:52 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Mon, 4 Dec 2017 17:12:52 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 053BE1A01B8; Mon, 4 Dec 2017 17:12:52 +0900 (JST) From: Keiji Hayashibara To: robh+dt@kernel.org, mark.rutland@arm.com Cc: linux@armlinux.org.uk, yamada.masahiro@socionext.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, masami.hiramatsu@linaro.org, jaswinder.singh@linaro.org, hayashi.kunihiko@socionext.com, owada.kiyoshi@socionext.com, Keiji Hayashibara Subject: [PATCH] arm: dts: uniphier: add efuse node for UniPhier 32bit SoC Date: Mon, 4 Dec 2017 17:12:10 +0900 Message-Id: <1512375130-16860-1-git-send-email-hayashibara.keiji@socionext.com> X-Mailer: git-send-email 2.7.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add efuse node for UniPhier LD4, Pro4, sLD8, Pro5 and PXs2. This efuse node is included in soc-glue. Signed-off-by: Keiji Hayashibara --- arch/arm/boot/dts/uniphier-ld4.dtsi | 18 ++++++++++++++++++ arch/arm/boot/dts/uniphier-pro4.dtsi | 23 +++++++++++++++++++++++ arch/arm/boot/dts/uniphier-pro5.dtsi | 33 +++++++++++++++++++++++++++++++++ arch/arm/boot/dts/uniphier-pxs2.dtsi | 18 ++++++++++++++++++ arch/arm/boot/dts/uniphier-sld8.dtsi | 18 ++++++++++++++++++ 5 files changed, 110 insertions(+) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi index 01fc3e1..6883f3b 100644 --- a/arch/arm/boot/dts/uniphier-ld4.dtsi +++ b/arch/arm/boot/dts/uniphier-ld4.dtsi @@ -273,6 +273,24 @@ }; }; + soc-glue@5f900000 { + compatible = "socionext,uniphier-ld4-soc-glue-debug", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x5f900000 0x2000>; + + efuse@100 { + compatible = "socionext,uniphier-efuse"; + reg = <0x100 0x28>; + }; + + efuse@130 { + compatible = "socionext,uniphier-efuse"; + reg = <0x130 0x8>; + }; + }; + timer@60000200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x60000200 0x20>; diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi index 7955c3a..150726b 100644 --- a/arch/arm/boot/dts/uniphier-pro4.dtsi +++ b/arch/arm/boot/dts/uniphier-pro4.dtsi @@ -294,6 +294,29 @@ }; }; + soc-glue@5f900000 { + compatible = "socionext,uniphier-pro4-soc-glue-debug", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x5f900000 0x2000>; + + efuse@100 { + compatible = "socionext,uniphier-efuse"; + reg = <0x100 0x28>; + }; + + efuse@130 { + compatible = "socionext,uniphier-efuse"; + reg = <0x130 0x8>; + }; + + efuse@200 { + compatible = "socionext,uniphier-efuse"; + reg = <0x200 0x14>; + }; + }; + aidet: aidet@5fc20000 { compatible = "socionext,uniphier-pro4-aidet"; reg = <0x5fc20000 0x200>; diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi index 6589b8a..f291dd6 100644 --- a/arch/arm/boot/dts/uniphier-pro5.dtsi +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi @@ -355,6 +355,39 @@ }; }; + soc-glue@5f900000 { + compatible = "socionext,uniphier-pro5-soc-glue-debug", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x5f900000 0x2000>; + + efuse@100 { + compatible = "socionext,uniphier-efuse"; + reg = <0x100 0x28>; + }; + + efuse@130 { + compatible = "socionext,uniphier-efuse"; + reg = <0x130 0x8>; + }; + + efuse@200 { + compatible = "socionext,uniphier-efuse"; + reg = <0x200 0x28>; + }; + + efuse@300 { + compatible = "socionext,uniphier-efuse"; + reg = <0x300 0x14>; + }; + + efuse@400 { + compatible = "socionext,uniphier-efuse"; + reg = <0x400 0x8>; + }; + }; + aidet: aidet@5fc20000 { compatible = "socionext,uniphier-pro5-aidet"; reg = <0x5fc20000 0x200>; diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi index d82d6d8..8e54e87 100644 --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi @@ -375,6 +375,24 @@ }; }; + soc-glue@5f900000 { + compatible = "socionext,uniphier-pxs2-soc-glue-debug", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x5f900000 0x2000>; + + efuse@100 { + compatible = "socionext,uniphier-efuse"; + reg = <0x100 0x28>; + }; + + efuse@200 { + compatible = "socionext,uniphier-efuse"; + reg = <0x200 0x58>; + }; + }; + aidet: aidet@5fc20000 { compatible = "socionext,uniphier-pxs2-aidet"; reg = <0x5fc20000 0x200>; diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi index 7188536..afafe7c 100644 --- a/arch/arm/boot/dts/uniphier-sld8.dtsi +++ b/arch/arm/boot/dts/uniphier-sld8.dtsi @@ -277,6 +277,24 @@ }; }; + soc-glue@5f900000 { + compatible = "socionext,uniphier-sld8-soc-glue-debug", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x5f900000 0x2000>; + + efuse@100 { + compatible = "socionext,uniphier-efuse"; + reg = <0x100 0x28>; + }; + + efuse@200 { + compatible = "socionext,uniphier-efuse"; + reg = <0x200 0x14>; + }; + }; + timer@60000200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x60000200 0x20>;