From patchwork Tue Nov 14 08:52:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 118860 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp2784677qgn; Tue, 14 Nov 2017 00:53:45 -0800 (PST) X-Google-Smtp-Source: AGs4zMakxyHoYQVLz5F2w0i7d6Q0iReOTD0jz5qIsEXqUtHcwcNUBMlseDPUZpq1jDN+DaYhtLMI X-Received: by 10.99.183.10 with SMTP id t10mr11726527pgf.128.1510649625766; Tue, 14 Nov 2017 00:53:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510649625; cv=none; d=google.com; s=arc-20160816; b=TLt6L0mBQsSBgDpvW5BuGeIgo96b/wpz9fCLSLQHuuV2m9qkn30bsqStUbC/Q9r9+A PTUc0v7py+ueb+FaEhacL7AhqeUNZVob1Mhvt8LbWQPEj8o2fWwul66LutDHii2ISWG2 4I4dtySpKxhysmFJHqSlIgZwcGZ2W48D8ieQQUA1rigJriKvJ1Kow7iVKHbBlUyei22Z QZiDyqXA9aeZsQr5sGCfxzID2Pm80BFDRJBLEoO0wmvIIbaUcPV+bkBlWsoSf85xRTSU ri9G2Tbs+9m1Kfqd1TmCwojNMhGi7syLRLy5T9H+0DsInGAf9VVgI96HtoRBZrzP3E2E ZwCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=Cm0JfxckbGav8Cmdlx5T5an8Ik1pC44e2Qhy4UDL8kc=; b=vaesh4IPcTaAKs0LTBc8aV2MhrH/rfeSiEQcKvlVLeagNGudo1FXVIR0tPfAeqk0xa izfTTuS+dUUvK0vvZhhfoBW+bS4FZB3kXFx4dPTEu30CQBHsjz10vSIocxRKSk8ONKKs 4Ov1vOizC6VcfAtxW1EjW9yK1zhDQgRMFpDcjWNy+TT4fO1D3JuQfdrb9o9jCCTwhfNh LMcdQcVp43Izh8KHDkZQEFX8H4I9LZPDQ2CU48vCW2hL1dZm5hcnpHgjAdd6WWuO8hZu lKLfSJ9pnkaytYYObCqEbaUWTYq1rE9dKmmUtFpSxOTmHQbd8HyWl2MDGnensihSy5kv Y5Vg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Tfv2qya1; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x8si11130279pgq.460.2017.11.14.00.53.45; Tue, 14 Nov 2017 00:53:45 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Tfv2qya1; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753592AbdKNIxm (ORCPT + 6 others); Tue, 14 Nov 2017 03:53:42 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:40712 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752952AbdKNIx3 (ORCPT ); Tue, 14 Nov 2017 03:53:29 -0500 Received: by mail-wm0-f66.google.com with SMTP id b189so12901367wmd.5 for ; Tue, 14 Nov 2017 00:53:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IPOdwj6QrGu1gx7nMpbAZwlPQlpdDW1hnIoGbpw7W9E=; b=Tfv2qya1pZ9agEG1lzIv1k7eyIacKP1fsh2qwCI6QUOkaTFUxFLkos0b+rDbV/8WLB tc1whMfAEaYCOztSkR7ulrLonbxmUBALAw+/1HCszfZdaK4eiZ1xYxy6AotCXBRUyVq4 iXZlABLUE947Ckrzd2xwNaxt4sLJZNLkAVnUw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IPOdwj6QrGu1gx7nMpbAZwlPQlpdDW1hnIoGbpw7W9E=; b=XHWcXvX+fGGITfmgDCmIOYH3/okX2q3Lbbazz6uQRhIkYGESkMDWL3TX5AXBuYcuqX 3fjp6uFz1K1TAtcAVx4ZYf51aM48LOOkfkzJ2EE64nk609wHEAglhB2JOYoXIbeqcVeD vl1qRg3kHvx+QUXgPkzwC6bqCdVGXaYbObTLz9AwKwP9OcgNwsIdnihdriC+cdNfrl0Z T1Qwa9dPfNvlHF3kd45QadPqU/WK0Uwr0giiNhMK8uKp7owzVd7+F2gjaJ1VGQBcYa58 fWseqMKk/663sOjzWDTVZUZmcbh38TNCcO9y65QwZQg7Zohw7b3Yif8/r+GQ6tStl560 bFtA== X-Gm-Message-State: AJaThX55Y7AgJvso7aCJ/ZLT2wO5wOx+AG/CY61ItC9LG7XEdD+UXuMy +9pW0F2ALFZRZzh/JvGnVF4mag== X-Received: by 10.28.30.2 with SMTP id e2mr8195102wme.36.1510649607832; Tue, 14 Nov 2017 00:53:27 -0800 (PST) Received: from lmecxl0911.lme.st.com ([80.215.205.30]) by smtp.gmail.com with ESMTPSA id g28sm22894551wra.31.2017.11.14.00.53.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 14 Nov 2017 00:53:27 -0800 (PST) From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, ludovic.barre@st.com, julien.thierry@arm.com, sudeep.holla@arm.com, arnd@arndb.de Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v8 4/6] clocksource: stm32: only use 32 bits timers Date: Tue, 14 Nov 2017 09:52:41 +0100 Message-Id: <1510649563-22975-5-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510649563-22975-1-git-send-email-benjamin.gaignard@linaro.org> References: <1510649563-22975-1-git-send-email-benjamin.gaignard@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The clock driving counters is at 90MHz so the maximum period for 16 bis counters is around 750 ms which is a short period for a clocksource. For 32 bits counters this period is close 47 secondes which is more acceptable. This patch remove 16 bits counters support and makes sure that they won't be probed anymore. Signed-off-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index ae41a19..8173bcf 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -83,9 +83,9 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) static int __init stm32_clockevent_init(struct device_node *node) { struct reset_control *rstc; - unsigned long max_delta; - int ret, bits, prescaler = 1; + unsigned long max_arr; struct timer_of *to; + int ret; to = kzalloc(sizeof(*to), GFP_KERNEL); if (!to) @@ -115,29 +115,27 @@ static int __init stm32_clockevent_init(struct device_node *node) /* Detect whether the timer is 16 or 32 bits */ writel_relaxed(~0U, timer_of_base(to) + TIM_ARR); - max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR); - if (max_delta == ~0U) { - prescaler = 1; - bits = 32; - } else { - prescaler = 1024; - bits = 16; + max_arr = readl_relaxed(timer_of_base(to) + TIM_ARR); + if (max_arr != ~0U) { + pr_err("32 bits timer is needed\n"); + ret = -EINVAL; + goto deinit; } + writel_relaxed(0, timer_of_base(to) + TIM_ARR); - writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC); + writel_relaxed(0, timer_of_base(to) + TIM_PSC); writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER); writel_relaxed(0, timer_of_base(to) + TIM_SR); clockevents_config_and_register(&to->clkevt, - timer_of_period(to), MIN_DELTA, max_delta); - - pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n", - node, bits); + timer_of_period(to), MIN_DELTA, ~0U); return 0; +deinit: + timer_of_exit(to); err: kfree(to); return ret;