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[209.132.180.67]) by mx.google.com with ESMTP id b4si2002571pfj.87.2017.08.29.02.35.49; Tue, 29 Aug 2017 02:35:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=YfqzHefI; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751355AbdH2Jfs (ORCPT + 6 others); Tue, 29 Aug 2017 05:35:48 -0400 Received: from mail-wm0-f48.google.com ([74.125.82.48]:33392 "EHLO mail-wm0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751227AbdH2Jfr (ORCPT ); Tue, 29 Aug 2017 05:35:47 -0400 Received: by mail-wm0-f48.google.com with SMTP id b14so18796792wme.0 for ; Tue, 29 Aug 2017 02:35:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OhzhjGoVjNsRobb84pBEAw6JcQXRvH0PdGogBMKgdPc=; b=YfqzHefIteA/tsBkVY2vL91PnjqLdaz4B5181dSdPjhxwffgdlyvTKTCunNh25kJFC LKwzWogzZMg6pHM2OJ0q2t7pYsiHoiT7IYq7aAWsp2krpCKC23zem/HHd+kjmHp6QEQy s6pGXCuk5zX7wSHYuXBOvpL6YY93c4PYV5nwo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OhzhjGoVjNsRobb84pBEAw6JcQXRvH0PdGogBMKgdPc=; b=l+zRv4fpQfzoAuaBvNQ8Y9fBje6+cgFdKKGEOZuiwVkIupz6fLbLayPKRf44Mlju2d FHMltbW2JuSPBmFcDILAoNDlA+kO2RGWGKT0xhTWjTt617FXARywX/0bfvXBIeqRTLWQ re2JsULBHvTdWjKx0yMytKl+6biB6CzseI9ZdWu2sd2cOCo8UZB+7eQ+i6u/Vb0qxUU4 HOHo695xzv0FD6dOsZRLtEMRScknDydbASlzfErcEOu+BKFHkbps1UonBn9q5mFRYNE8 gAY2VewtXKQ3ljWUWIkYY5ab6Ort4kNBFctxcinU0qWdS2eqb2dniBhWCU+UiAC74mBv szww== X-Gm-Message-State: AHYfb5ju9xjT8CctswU1lQlE5GeS6oxTAiJLodTuZC+65DEoge5Z3L6z QkY2sERJbw/g6lr6Z660lw== X-Received: by 10.28.187.4 with SMTP id l4mr1915456wmf.168.1503999346620; Tue, 29 Aug 2017 02:35:46 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:cc22:a7ba:e8a7:7caf]) by smtp.gmail.com with ESMTPSA id r18sm3621775wrc.44.2017.08.29.02.35.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 29 Aug 2017 02:35:45 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dong Aisheng , Mark Rutland , devicetree@vger.kernel.org, Shawn Guo , Bai Ping , Rob Herring , Rob Herring Subject: [PATCH 1/9] dt-bindings: timer: Add nxp tpm timer binding doc Date: Tue, 29 Aug 2017 11:34:19 +0200 Message-Id: <1503999271-15712-1-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <20170829093354.GA2572@mai> References: <20170829093354.GA2572@mai> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Dong Aisheng Adding NXP Low Power Timer/Pulse Width Modulation Module (TPM) binding doc. Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: Daniel Lezcano Cc: Thomas Gleixner Cc: Shawn Guo Cc: Bai Ping Acked-by: Rob Herring Signed-off-by: Dong Aisheng Signed-off-by: Daniel Lezcano --- .../devicetree/bindings/timer/nxp,tpm-timer.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt new file mode 100644 index 0000000..b4aa7dd --- /dev/null +++ b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt @@ -0,0 +1,28 @@ +NXP Low Power Timer/Pulse Width Modulation Module (TPM) + +The Timer/PWM Module (TPM) supports input capture, output compare, +and the generation of PWM signals to control electric motor and power +management applications. The counter, compare and capture registers +are clocked by an asynchronous clock that can remain enabled in low +power modes. TPM can support global counter bus where one TPM drives +the counter bus for the others, provided bit width is the same. + +Required properties: + +- compatible : should be "fsl,imx7ulp-tpm" +- reg : Specifies base physical address and size of the register sets + for the clock event device and clock source device. +- interrupts : Should be the clock event device interrupt. +- clocks : The clocks provided by the SoC to drive the timer, must contain + an entry for each entry in clock-names. +- clock-names : Must include the following entries: "igp" and "per". + +Example: +tpm5: tpm@40260000 { + compatible = "fsl,imx7ulp-tpm"; + reg = <0x40260000 0x1000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>, + <&clks IMX7ULP_CLK_LPTPM5>; + clock-names = "ipg", "per"; +};