From patchwork Thu Jun 29 02:54:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 106591 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp605541qge; Wed, 28 Jun 2017 19:55:33 -0700 (PDT) X-Received: by 10.99.111.132 with SMTP id k126mr13670740pgc.76.1498704933338; Wed, 28 Jun 2017 19:55:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1498704933; cv=none; d=google.com; s=arc-20160816; b=OFoWTkirpRz3jF0XwQKA7pmKDg+IRb3EfpQhHQ6+I3AcQ+kvCHMMRQJFj4uy1lvS76 A7X0QT7uKggC6QJSch/dQcVr3BTqeaqExF1fHSc/PV7hk22J/1a9LO9oMiqKfTei2Lwe rUi7GBn20MIhFmImEWHAM6myKUtUDd1mRodeYS118Qz+uG5J/uWFbDPOgVH3JEryarh6 5mMOJIhSPAn8P66PLD4/QVoVppsZ8rdaDY7NskzPV/48HUL/rM9eMK2nPdPmhwt/n1f+ FD0Xcbbn+OTlfENpnOr5iHv500/OZOw3K4w5HPZNjIPR3OkRbi89+PtdoEsr/mxN6Jum tAlw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dmarc-filter:arc-authentication-results; bh=ZKWBTngGxBSi1EdHpI6Q3Y55RQ/ttoV33ZYugCvbbcc=; b=td87FhJXiiCOubPCoP5QYUC2rnUFwmkWJcT4X4cx3ee+SJOpy60WjL5j6WRvUCA+vt htRNUj/sRcgL/gRD8IOzI9ezU57tPLR8wRDQwxIOB/yYjSEnxDH3AVhtX2IRrOv2K4HN 5qKFjTt3oTDNKEPV64X7nZQh/ySMh+H1yNQYn+8S7FvA2T5+zJZuDkoX0s5h273i767y pLlOey3sqoUzif7726P9as5eFGPsN9ra9DHJ7uXLioQ0cty7a0HWANjAiBckeLyN75Im StH+Gk8GB7VJ9d/FxS3sE2cJEtcig4l9g58oIY0yMGwg+OCToFW9Fw/4Wmu6atRhcwBR 84HQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a20si2780529pfc.137.2017.06.28.19.55.33; Wed, 28 Jun 2017 19:55:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751630AbdF2Cz0 (ORCPT + 7 others); Wed, 28 Jun 2017 22:55:26 -0400 Received: from mail.kernel.org ([198.145.29.99]:50168 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751548AbdF2CzZ (ORCPT ); Wed, 28 Jun 2017 22:55:25 -0400 Received: from localhost.localdomain (li411-102.members.linode.com [106.187.91.102]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 9927C22BD9; Thu, 29 Jun 2017 02:55:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9927C22BD9 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=shawnguo@kernel.org From: Shawn Guo To: Thierry Reding , Rob Herring Cc: Baoyou Xie , Xin Zhou , Jun Nie , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Shawn Guo Subject: [PATCH 1/2] dt-bindings: pwm: add bindings doc for ZTE ZX PWM controller Date: Thu, 29 Jun 2017 10:54:33 +0800 Message-Id: <1498704874-14599-2-git-send-email-shawnguo@kernel.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1498704874-14599-1-git-send-email-shawnguo@kernel.org> References: <1498704874-14599-1-git-send-email-shawnguo@kernel.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Shawn Guo It adds bindings document for ZTE ZX PWM controller. The device has two clocks: PCLK and WCLK. The PCLK is for register access, and WCLK is the reference clock for calculating period and duty cycles. Also, the device supports polarity configuration, so #pwm-cells should be 3. Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/pwm/pwm-zx.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-zx.txt -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/pwm/pwm-zx.txt b/Documentation/devicetree/bindings/pwm/pwm-zx.txt new file mode 100644 index 000000000000..a6bcc75c9164 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-zx.txt @@ -0,0 +1,22 @@ +ZTE ZX PWM controller + +Required properties: + - compatible: Should be "zte,zx296718-pwm". + - reg: Physical base address and length of the controller's registers. + - clocks : The phandle and specifier referencing the controller's clocks. + - clock-names: "pclk" for PCLK, "wclk" for WCLK to the PWM controller. The + PCLK is for register access, while WCLK is the reference clock for + calculating period and duty cycles. + - #pwm-cells: Should be 3. See pwm.txt in this directory for a description of + the cells format. + +Example: + + pwm: pwm@1439000 { + compatible = "zte,zx296718-pwm"; + reg = <0x1439000 0x1000>; + clocks = <&lsp1crm LSP1_PWM_PCLK>, + <&lsp1crm LSP1_PWM_WCLK>; + clock-names = "pclk", "wclk"; + #pwm-cells = <3>; + };