From patchwork Wed May 31 01:45:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhangfei Gao X-Patchwork-Id: 100734 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp113904qge; Tue, 30 May 2017 18:46:10 -0700 (PDT) X-Received: by 10.99.114.11 with SMTP id n11mr29103615pgc.4.1496195170094; Tue, 30 May 2017 18:46:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496195170; cv=none; d=google.com; s=arc-20160816; b=BQh8iFZ7Fh/4FmLeqlYd1IrKsHlSLp8u1Mdrsi+kZSPflTEIc9eECCORTgiV2au2NY ThhbA7GqRqWBjsjbgU6BzAUEZsnvCcXu5uRKtHZyDWuJLxM7MvsbHmssVeXM71LsqiDM ibrEVkDWmouTcEwxKOPVGZr6sPVYGX8a2+r7hsA6J4dHSJwCx8yEGoxaurGswU/HiAl+ M4G5XnfEYa7QuPwp/5B4OiA11NecozT5oXMWCpbhefkPNDg0GiCsP/eOwUINVZxtag26 o7lK7rR05Ox8xwoB1AwYMOHSGQ2LE4HWUwYlQv4fkrEkjqSmakeJTjcTGf+oCBvFv2NA ZtKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=QlIjdM+43iCBZ2gcqN6BwLfypUJ6H4fOeI5fkQ2g40Q=; b=FqCHtNEgSZDv5rgc3NHNRmC+NGWJHgYIrtbJGi1HQ3Sa4YE9OsUCXgt/jmFiJ2x9x6 SUTkRoZ4VexYdJswgH2Z0MmzQHzwTzZY4EzfPY9Qcn71kfEc+ReU8by6ppc/6siwUMDD GD3GN6qzChqSsBbS8pCM8S8NXIc9/QOdj7kvoKCSysHsTz1IgfFKKQQzB5SpOI9tJQfD ORs8pe+ECwUVAgtRjCFezoKOAmSdCaMIX/MsA/dzQtqqobX5pwimAk1PVXxCVpwPsPKI Kv6v/OofA1w88uDSmXqFb9hBRx6edWMR8QsxdDhvbpjx7NnB8ybl7aO3WX+ZUGCrV8XK sy+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n26si14811741pgc.274.2017.05.30.18.46.09; Tue, 30 May 2017 18:46:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751101AbdEaBqI (ORCPT + 7 others); Tue, 30 May 2017 21:46:08 -0400 Received: from mail-pg0-f42.google.com ([74.125.83.42]:33947 "EHLO mail-pg0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751025AbdEaBqI (ORCPT ); Tue, 30 May 2017 21:46:08 -0400 Received: by mail-pg0-f42.google.com with SMTP id u28so394147pgn.1 for ; Tue, 30 May 2017 18:46:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=h5Uzb1JFq2gAEWFvRbACP69gM6zwd2BxyfvjNAZ9DWY=; b=QPRhVwudZpmLDkQMOBs68tJEJoeGJEqKdBg8cdsuCD4IijrQKGlX+EnDQEvpdEoHeB elg1N00hxEaN3XeR4eifNmyHsKwlIZ9x4UiXYAJKXJLluEc76nNS13u7FJfXzDPDC4td EtK673hPRMW4JF+fiw/JTsbwNWYQbSAJS1QNk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=h5Uzb1JFq2gAEWFvRbACP69gM6zwd2BxyfvjNAZ9DWY=; b=XUU1+9myvtum2qcq7cTTeU3vf4I5afO56oA7gIIeeQe4YeYqEJr3ye7a4bFwOKMQrO y64o8Wl/2nLbD/SBAU4Qi5/CbOpEExjH8L/0Z1tQ5L0fnGpM8VOSz07ZsTH9LCBWoCPQ +gwRg0twQn+oL8R3H52EtdGCaSOgCKv4AoYAwVAD2UQ2/5Tv9gEaj69Rjre/WuQpzX+q 1YZz6AkQ3MOdN8kcyUmo0bHhcJzzY7Oe2nZthqsQOqAakyEFuzjJVJjBTl16FxYZooAf CMQGDbObdMOHVHEKO+VNizKpgZ1HvsAwrezMepLtPbAzChB+l85X5O8XbpUp5bxkhfA+ kQTw== X-Gm-Message-State: AODbwcCOHbT4mK/4uPbybKgWgFEpcKj6x3JXNxai7DvB7Kyj50bgP7qK UlZ8dzE+lH3ofads X-Received: by 10.98.13.220 with SMTP id 89mr27056962pfn.112.1496195167377; Tue, 30 May 2017 18:46:07 -0700 (PDT) Received: from localhost.localdomain ([36.5.161.58]) by smtp.gmail.com with ESMTPSA id r90sm24229395pfl.82.2017.05.30.18.46.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 30 May 2017 18:46:06 -0700 (PDT) From: Zhangfei Gao To: Stephen Boyd , Rob Herring , guodong Xu , xuwei5@hisilicon.com Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Zhangfei Gao , Li Pengcheng Subject: [Resend PATCH 1/2] clk: hi6220: add acpu clock Date: Wed, 31 May 2017 09:45:38 +0800 Message-Id: <1496195139-16687-1-git-send-email-zhangfei.gao@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add acpu clock, including sft clock controlling hi6220 coresight module Signed-off-by: Zhangfei Gao Signed-off-by: Li Pengcheng Acked-by: Rob Herring --- Verified on clk-next, v.12-rc1 .../devicetree/bindings/clock/hi6220-clock.txt | 1 + drivers/clk/hisilicon/clk-hi6220.c | 23 ++++++++++++++++++++++ include/dt-bindings/clock/hi6220-clock.h | 4 ++++ 3 files changed, 28 insertions(+) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/clock/hi6220-clock.txt b/Documentation/devicetree/bindings/clock/hi6220-clock.txt index e4d5fea..ef3deb7 100644 --- a/Documentation/devicetree/bindings/clock/hi6220-clock.txt +++ b/Documentation/devicetree/bindings/clock/hi6220-clock.txt @@ -11,6 +11,7 @@ Required Properties: - compatible: the compatible should be one of the following strings to indicate the clock controller functionality. + - "hisilicon,hi6220-acpu-sctrl" - "hisilicon,hi6220-aoctrl" - "hisilicon,hi6220-sysctrl" - "hisilicon,hi6220-mediactrl" diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c index 2ae151c..fc8813f 100644 --- a/drivers/clk/hisilicon/clk-hi6220.c +++ b/drivers/clk/hisilicon/clk-hi6220.c @@ -285,3 +285,26 @@ static void __init hi6220_clk_power_init(struct device_node *np) ARRAY_SIZE(hi6220_div_clks_power), clk_data); } CLK_OF_DECLARE(hi6220_clk_power, "hisilicon,hi6220-pmctrl", hi6220_clk_power_init); + + +/* clocks in acpu */ +static const struct hisi_gate_clock hi6220_acpu_sc_gate_sep_clks[] = { + { HI6220_ACPU_SFT_AT_S, "sft_at_s", "cs_atb", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0xc, 11, 0, }, +}; + +static void __init hi6220_clk_acpu_init(struct device_node *np) +{ + struct hisi_clock_data *clk_data; + int nr = ARRAY_SIZE(hi6220_acpu_sc_gate_sep_clks); + + clk_data = hisi_clk_init(np, nr); + if (!clk_data) + return; + + hisi_clk_register_gate_sep(hi6220_acpu_sc_gate_sep_clks, + ARRAY_SIZE(hi6220_acpu_sc_gate_sep_clks), + clk_data); +} + +CLK_OF_DECLARE(hi6220_clk_acpu, "hisilicon,hi6220-acpu-sctrl", hi6220_clk_acpu_init); diff --git a/include/dt-bindings/clock/hi6220-clock.h b/include/dt-bindings/clock/hi6220-clock.h index b8ba665..409cc02 100644 --- a/include/dt-bindings/clock/hi6220-clock.h +++ b/include/dt-bindings/clock/hi6220-clock.h @@ -174,4 +174,8 @@ #define HI6220_DDRC_AXI1 7 #define HI6220_POWER_NR_CLKS 8 + +/* clk in Hi6220 acpu sctrl */ +#define HI6220_ACPU_SFT_AT_S 0 + #endif