From patchwork Fri Mar 31 04:20:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 96343 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp550308qgd; Thu, 30 Mar 2017 21:21:47 -0700 (PDT) X-Received: by 10.98.204.195 with SMTP id j64mr865889pfk.213.1490934107419; Thu, 30 Mar 2017 21:21:47 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x2si3835985pls.270.2017.03.30.21.21.47; Thu, 30 Mar 2017 21:21:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750863AbdCaEVq (ORCPT + 7 others); Fri, 31 Mar 2017 00:21:46 -0400 Received: from conuserg-09.nifty.com ([210.131.2.76]:22538 "EHLO conuserg-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750763AbdCaEVq (ORCPT ); Fri, 31 Mar 2017 00:21:46 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id v2V4KsU0016072; Fri, 31 Mar 2017 13:20:54 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v2V4KsU0016072 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1490934055; bh=3VVTMiRh/qwsX5i998D2eB9HnLjOnAFTj+mTjWUaKzU=; h=From:To:Cc:Subject:Date:From; b=KhOsXljCWazWSpYc1Dc93r5djAL2eCMpqpUd5IQr0ogNP/54NGoPKc5eejde+hMcv pNvTsxvcAdRFyOWGWytwFeg65G84uUlZ8XnO3NXok+iJDyShDhTar/MeNX2yKpCbvE O39r7I2KPvTq9RZbP0Tv2OFKs868PSgW/ApVXsm99b4uICQtU2qPS2hmxH/hdE6SRQ msdjC2rBa73O+75vZpRewD52T1rK/WhIWdlvEIOz7um0o73QgshyJoVSoTOG7szdsd YHCBs2sePsZQ26pUc88ajixiVHX8gFVvetyqPA8LxNpPpnzd8pzh/uPO4Rz9bAC8Yx Ftuvh0sfZxKuA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: Piotr Sroka , Masahiro Yamada , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Will Deacon , Mark Rutland , Catalin Marinas , linux-arm-kernel@lists.infradead.org Subject: [PATCH] arm64: dts: uniphier: add input-delay properties to Cadence eMMC node Date: Fri, 31 Mar 2017 13:20:45 +0900 Message-Id: <1490934045-18874-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Since commit a04e2b383401 ("mmc: sdhci-cadence: Update PHY delay configuration"), PHY parameters must be specified by DT. The hard-coded settings have been converted as follows: - SDHCI_CDNS_PHY_DLY_SD_DEFAULT -> cdns,phy-input-delay-legacy - SDHCI_CDNS_PHY_DLY_EMMC_SDR -> cdns,phy-input-delay-mmc-highspeed - SDHCI_CDNS_PHY_DLY_EMMC_DDR -> cdns,phy-input-delay-mmc-ddr The following have not been moved: - SDHCI_CDNS_PHY_DLY_SD_HS this is unneeded in the eMMC configuration - SDHCI_CDNS_PHY_DLY_EMMC_LEGACY this is never enabled by the driver as it is covered by SDHCI_CDNS_PHY_DLY_SD_DEFAULT Signed-off-by: Masahiro Yamada --- arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 3 +++ arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 3 +++ 2 files changed, 6 insertions(+) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi index 5dc5124..b6ebdc9 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -310,6 +310,9 @@ bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; + cdns,phy-input-delay-legacy = <4>; + cdns,phy-input-delay-mmc-highspeed = <2>; + cdns,phy-input-delay-mmc-ddr = <3>; }; usb0: usb@5a800100 { diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index 6c9a72d..0ab6c2e 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -394,6 +394,9 @@ bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; + cdns,phy-input-delay-legacy = <4>; + cdns,phy-input-delay-mmc-highspeed = <2>; + cdns,phy-input-delay-mmc-ddr = <3>; }; sd: sdhc@5a400000 {