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[61.216.91.114]) by smtp.gmail.com with ESMTPSA id s13sm20541405pfk.26.2017.03.02.22.00.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 02 Mar 2017 22:00:36 -0800 (PST) From: Leo Yan To: Rob Herring , Mark Rutland , Wei Xu , Catalin Marinas , Will Deacon , Michael Turquette , Stephen Boyd , Mathieu Poirier , John Stultz , Guodong Xu , Haojian Zhuang , Greg Kroah-Hartman , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, mike.leach@linaro.org Cc: Leo Yan Subject: [PATCH v3 1/5] coresight: bindings for debug module Date: Fri, 3 Mar 2017 14:00:05 +0800 Message-Id: <1488520809-31670-2-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1488520809-31670-1-git-send-email-leo.yan@linaro.org> References: <1488520809-31670-1-git-send-email-leo.yan@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org According to ARMv8 architecture reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate debug module and it can support self-hosted debug and external debug. Especially for supporting self-hosted debug, this means the program can access the debug module from mmio region; and usually the mmio region is integrated with coresight. So add document for binding debug component, includes binding to APB clock; and also need specify the CPU node which the debug module is dedicated to specific CPU. Suggested-by: Mike Leach Reviewed-by: Mathieu Poirier Signed-off-by: Leo Yan --- .../devicetree/bindings/arm/coresight-debug.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/coresight-debug.txt -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/arm/coresight-debug.txt b/Documentation/devicetree/bindings/arm/coresight-debug.txt new file mode 100644 index 0000000..92e5003 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/coresight-debug.txt @@ -0,0 +1,40 @@ +* CoreSight Debug Component: + +CoreSight debug component are compliant with the ARMv8 architecture reference +manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The external debug +module is mainly used for two modes: self-hosted debug and external debug, and +it can be accessed from mmio region from Coresight and eventually the debug +module connects with CPU for debugging. And the debug module provides +sample-based profiling extension, which can be used to sample CPU program +counter, secure state and exception level, etc; usually every CPU has one +dedicated debug module to be connected. + +Required properties: + +- compatible : should be + * "arm,coresight-debug"; supplemented with "arm,primecell" since + this driver is using the AMBA bus interface. + +- reg : physical base address and length of the register set. + +- clocks : the clock associated to this component. + +- clock-names : the name of the clock referenced by the code. Since we are + using the AMBA framework, the name of the clock providing + the interconnect should be "apb_pclk" and the clock is + mandatory. The interface between the debug logic and the + processor core is clocked by the internal CPU clock, so it + is enabled with CPU clock by default. + +- cpu : the cpu phandle the debug module is affined to. When omitted + the module is considered to belong to CPU0. + +Example: + + debug@f6590000 { + compatible = "arm,coresight-debug","arm,primecell"; + reg = <0 0xf6590000 0 0x1000>; + clocks = <&sys_ctrl HI6220_DAPB_CLK>; + clock-names = "apb_pclk"; + cpu = <&cpu0>; + };