From patchwork Tue Feb 28 15:06:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 94638 Delivered-To: patch@linaro.org Received: by 10.140.20.113 with SMTP id 104csp1366046qgi; Tue, 28 Feb 2017 07:17:40 -0800 (PST) X-Received: by 10.98.86.68 with SMTP id k65mr3079111pfb.13.1488295060625; Tue, 28 Feb 2017 07:17:40 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s2si2047388pgd.4.2017.02.28.07.17.40; Tue, 28 Feb 2017 07:17:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751660AbdB1PRj (ORCPT + 7 others); Tue, 28 Feb 2017 10:17:39 -0500 Received: from mail-pf0-f180.google.com ([209.85.192.180]:34973 "EHLO mail-pf0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751135AbdB1PRi (ORCPT ); Tue, 28 Feb 2017 10:17:38 -0500 Received: by mail-pf0-f180.google.com with SMTP id j5so4886755pfb.2 for ; Tue, 28 Feb 2017 07:16:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=Cp7AuFlhtE4fJG8aY8VbshtYV847O7UW521FPWzisf8=; b=ACf32OpK0WBk7t5Mh837Rz7P+acfunxpXKBv8qp6xYSIAVWBN07yJt61XcscVrhD/+ bJNlplYTfJkkCdDHLaoFgNRLFZKmSzijjG4D7FRgoMiTT5yR2jrub/846sVsPwzijMSL yesQ3atO1Ieh2Y+VCNCO2rjnBEF2D6u91EShU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=Cp7AuFlhtE4fJG8aY8VbshtYV847O7UW521FPWzisf8=; b=pEnPy3go6NtoA+jkrsCMbDXIABxXbC9D6DIFUXj7X+zGRlmND2WbxBGz0yktbYetG6 audWRF4/7/8GO2qPAKct0GAwPc/j1Clw3/wSpK1/44/bH7JIWo5XwzvGBz0KfPoKmcm7 iCpX7PVKzGA1qNxjSdOWQifpvT+EjmtRrvkum8sMZeAkpKHUhAg2dRBs7zCCeHqntN27 bU7Ig+8R06aSeTXBHTXk2C1ojdusPjRwGy40526qu3RgwAYvNpKfjB3HGaEiSfff91aJ HOcneoFf0NxkhuRt0W8LmOYD+i9jmzKathS6WXqpNxszaMOmaDjOIPwXIbZIvdP0A9lq YilQ== X-Gm-Message-State: AMke39lu8Hep1zuk8crwizIGERXXTNrPDNIH5BfTfRqoMt2MoH4zWbasLi5+EY0Ga7w1+6Sd X-Received: by 10.84.208.227 with SMTP id c32mr3568510plj.71.1488294483770; Tue, 28 Feb 2017 07:08:03 -0800 (PST) Received: from localhost.localdomain ([103.192.224.50]) by smtp.gmail.com with ESMTPSA id c64sm4926145pfa.45.2017.02.28.07.07.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 28 Feb 2017 07:08:02 -0800 (PST) From: Leo Yan To: Rob Herring , Mark Rutland , Mathieu Poirier , Leo Yan , Greg Kroah-Hartman , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org Subject: [PATCH v2 1/3] coresight: bindings for debug module Date: Tue, 28 Feb 2017 23:06:58 +0800 Message-Id: <1488294420-14188-2-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1488294420-14188-1-git-send-email-leo.yan@linaro.org> References: <1488294420-14188-1-git-send-email-leo.yan@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org According to ARMv8 architecture reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate debug module and it can support self-hosted debug and external debug. Especially for supporting self-hosted debug, this means the program can access the debug module from mmio region; and usually the mmio region is integrated with coresight. So add document for binding debug component, includes binding to APB clock; and also need specify the CPU node which the debug module is dedicated to specific CPU. Suggested-by: Mike Leach Signed-off-by: Leo Yan --- .../devicetree/bindings/arm/coresight-debug.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/coresight-debug.txt -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/arm/coresight-debug.txt b/Documentation/devicetree/bindings/arm/coresight-debug.txt new file mode 100644 index 0000000..89820d5 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/coresight-debug.txt @@ -0,0 +1,40 @@ +* CoreSight Debug Component: + +CoreSight debug component are compliant with the ARMv8 architecture reference +manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The external debug +module is mainly used for two modes: self-hosted debug and external debug, and +it can be accessed from mmio region from Coresight and eventually the debug +module connects with CPU for debugging. And the debug module provides +sample-based profiling extension, which can be used to sample CPU program +counter, secure state and exception level, etc; usually every CPU has one +dedicated debug module to be connected. + +Required properties: + +- compatible : should be + * "arm,coresight-debug", "arm,primecell"; supplemented with + "arm,primecell" as driver is using the AMBA bus interface. + +- reg : physical base address and length of the register set. + +- clocks : the clock associated to this component. + +- clock-names : the name of the clock referenced by the code. Since we are + using the AMBA framework, the name of the clock providing + the interconnect should be "apb_pclk" and the clock is + mandatory. The interface between the debug logic and the + processor core is clocked by the internal CPU clock, so it + is enabled with CPU clock by default. + +- cpu : the cpu phandle the debug module is affined to. When omitted + the source is considered to belong to CPU0. + +Example: + + debug@f6590000 { + compatible = "arm,coresight-debug","arm,primecell"; + reg = <0 0xf6590000 0 0x1000>; + clocks = <&sys_ctrl HI6220_DAPB_CLK>; + clock-names = "apb_pclk"; + cpu = <&cpu0>; + };