From patchwork Thu Feb 23 01:57:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 94366 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp17920qgi; Wed, 22 Feb 2017 18:00:12 -0800 (PST) X-Received: by 10.98.209.16 with SMTP id z16mr43186333pfg.139.1487815212284; Wed, 22 Feb 2017 18:00:12 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y6si2796229pgc.350.2017.02.22.18.00.12; Wed, 22 Feb 2017 18:00:12 -0800 (PST) Received-SPF: temperror (google.com: error in processing during lookup of devicetree-owner@vger.kernel.org: DNS error) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=temperror (google.com: error in processing during lookup of devicetree-owner@vger.kernel.org: DNS error) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932465AbdBWB7v (ORCPT + 7 others); Wed, 22 Feb 2017 20:59:51 -0500 Received: from mail-pf0-f174.google.com ([209.85.192.174]:34042 "EHLO mail-pf0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934208AbdBWB7q (ORCPT ); Wed, 22 Feb 2017 20:59:46 -0500 Received: by mail-pf0-f174.google.com with SMTP id p185so1311031pfb.1 for ; Wed, 22 Feb 2017 17:59:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=sCrDMeK0074weCwVbySmoKPIGbbHDITWig/YIfboOOI=; b=HVC2CPZmhT5WFwP3XIiQQRAMQu/8kXTiWdRemr8MjhMVks23YXlWNzPudBGlPBoOJc YmLg6gk04p3K0UtvnUkqhePoturLjVc6IRF1beAV2gD6H3oj0+D4c/HqTYW6zQpU2MB1 +AWhM4KukYsBfiF053wEDFxQIJvWn6TRYLeuI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=sCrDMeK0074weCwVbySmoKPIGbbHDITWig/YIfboOOI=; b=TFqJ6Khd3f3fXTE+Mszz2bdJjoq9XIwgZAm4uIDAR6QwqvmaI7hX+lSzFP/ii2F+qW 9Bc6jnFSFh+hMW0XiFb2m8wE+Zjn3a+iLrqMp0gav0Eznlr5FFdBTcETmZ0cEY+Q9MWE MBIH2cdGpkpZMlngLaIQRB5K0UwTcbFMhHWCmKwfM2iD8riA6/3Uj8yi7Ev8TYPD9FvC Uhfz/xRR7iliVdGmsjjRrAKvIOerF+/pLstrGQNLfqQyFBmfuwMODXHkFr2opwDsjERP DBJvfCbw1yQS74OwmkeYOYAusiBDym61mIj5/aRRt35jRD6f917RYTbir/CRSpvdczA8 umQQ== X-Gm-Message-State: AMke39lhbp2qpDMfovWv7wBgUFWJ696KzHi8r8wI3h0/WvGS7NU9FPn8VB2g0edyScO7FwlG X-Received: by 10.99.215.5 with SMTP id d5mr46122276pgg.51.1487815185641; Wed, 22 Feb 2017 17:59:45 -0800 (PST) Received: from localhost.localdomain ([103.192.224.50]) by smtp.gmail.com with ESMTPSA id y67sm5830689pfa.96.2017.02.22.17.59.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 22 Feb 2017 17:59:44 -0800 (PST) From: Leo Yan To: Rob Herring , Mark Rutland , Mathieu Poirier , Leo Yan , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org Subject: [PATCH v1 1/2] coresight: bindings for debug module Date: Thu, 23 Feb 2017 09:57:46 +0800 Message-Id: <1487815067-27511-2-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487815067-27511-1-git-send-email-leo.yan@linaro.org> References: <1487815067-27511-1-git-send-email-leo.yan@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org According to ARMv8 architecture reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate debug module and it can support self-hosted debug and external debug. Especially for supporting self-hosted debug, this means the program can access the debug module from mmio region; and usually the mmio region is integrated with coresight. So add document for binding debug component, includes binding to two clocks, one is apb clock for bus and another is debug clock for debug module self; and also need specify the CPU node which the debug module is dedicated to specific CPU. Signed-off-by: Leo Yan --- .../devicetree/bindings/arm/coresight-debug.txt | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/coresight-debug.txt -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/arm/coresight-debug.txt b/Documentation/devicetree/bindings/arm/coresight-debug.txt new file mode 100644 index 0000000..6e03e9b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/coresight-debug.txt @@ -0,0 +1,39 @@ +* CoreSight Debug Component: + +CoreSight debug component are compliant with the ARMv8 architecture reference +manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The external debug +module is mainly used for two modes: self-hosted debug and external debug, and +it can be accessed from mmio region from Coresight and eventually the debug +module connects with CPU for debugging. And the debug module provides +sample-based profiling extension, which can be used to sample CPU program +counter, secure state and exception level, etc; usually every CPU has one +dedicated debug module to be connected. + +Required properties: + +- compatible : should be + * "arm,coresight-debug", "arm,primecell"; supplemented with + "arm,primecell" as driver is using the AMBA bus interface. + +- reg : physical base address and length of the register set. + +- clocks : the clocks associated to this component. + +- clock-names : the name of the clocks referenced by the code. Since we are + using the AMBA framework, the name of the clock providing + the interconnect should be "apb_pclk", and the debug module + has an additional clock "dbg_clk", which is used to provide + clock for debug module itself. Both clocks are mandatory. + +- cpu : the cpu phandle the debug module is affined to. When omitted + the source is considered to belong to CPU0. + +Example: + + debug@f6590000 { + compatible = "arm,coresight-debug","arm,primecell"; + reg = <0 0xf6590000 0 0x1000>; + clocks = <&sys_ctrl HI6220_CS_ATB>, <&acpu_ctrl HI6220_ACPU_DBG_CLK0>; + clock-names = "apb_pclk", "dbg_clk"; + cpu = <&cpu0>; + };