From patchwork Wed Jan 18 13:19:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 91778 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp1011091qgi; Wed, 18 Jan 2017 05:22:42 -0800 (PST) X-Received: by 10.84.131.2 with SMTP id 2mr5199835pld.45.1484745762132; Wed, 18 Jan 2017 05:22:42 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s2si213603pfb.210.2017.01.18.05.22.41; Wed, 18 Jan 2017 05:22:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@baylibre-com.20150623.gappssmtp.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752905AbdARNUh (ORCPT + 7 others); Wed, 18 Jan 2017 08:20:37 -0500 Received: from mail-wm0-f54.google.com ([74.125.82.54]:37243 "EHLO mail-wm0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752791AbdARNUc (ORCPT ); Wed, 18 Jan 2017 08:20:32 -0500 Received: by mail-wm0-f54.google.com with SMTP id c206so24765718wme.0 for ; Wed, 18 Jan 2017 05:20:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gjYAUx7cCSy+KrACbqFxG1BPaNYntYNoHa+KVUCPqgQ=; b=OQRrxnDyQnpdGHpEwa6I/wY/P2xoMPLX+8Z9Y8uea+ySpzakBkHRTcLIKOokWJUtzW 9uUYHPsEnmFNMDqwNorcHejD+ypqrd6cNYRQVx6UE9ESXipAnwPD5P/unBKohZXpHNVH 27SxCJBX+9AzI3a3Z0nTx6gUh8FTbzx9fnv57Feo6UzuRKnQzKt/fBJ0OF0sbiYy+e0B tYU0IQCQ5Qtj91bwb1tWc2eROmGVCM1vYokjUwGZaQhNMUISlSnsAuhSBI42PZOGzcda NoeVWOGMsdPDnTu37D9XVrrFG1QYc9hWyXrnO2CiGM9/51ZDnrpzEfgm5+QeLeQfzMqA i98Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gjYAUx7cCSy+KrACbqFxG1BPaNYntYNoHa+KVUCPqgQ=; b=VjjaBxNwsFpwyIUx7hThzYI2dhF3OfMvnCoKeRmoCXxyIQq6+RhVuaM6NAi8cH8big A8EUE21DEK30mPk9VNS52BZYuC6Tp2MLWeJEiExShJWdxBKj4HhdPYsf0VeeTfBSX2v/ f0bhpR26IX27nPNtaQ/FrK+aOkdeulm6ZGPxNyAeHMuDZj+CXWe/FgN2VsGWXw1rPeE8 Czu6UsAp95Zpoi6Gj89qlwLrwaZeUDK3CsWQuYO2o0jk19R8UdDUHZw9UCF7FJvaM/DU wlGnHwsOkP3+SPMgdOGcgvJzpv4qIiKBi66SniygiiZzoxvY6Dia2AsXfdyhB5mZnEkR AAOA== X-Gm-Message-State: AIkVDXLw0y68yijbr5We3uJh2zDzL7RNrhlfDxX+lo3iZHWc0HdgUG+oO9IYZ0Sl6H2V8pBS X-Received: by 10.28.191.139 with SMTP id o11mr22358455wmi.97.1484745630639; Wed, 18 Jan 2017 05:20:30 -0800 (PST) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id w79sm4899569wmw.0.2017.01.18.05.20.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Jan 2017 05:20:29 -0800 (PST) From: Bartosz Golaszewski To: Kevin Hilman , Sekhar Nori , Patrick Titiano , Michael Turquette , Tejun Heo , Rob Herring , Mark Rutland , Russell King , David Lechner Cc: linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bartosz Golaszewski Subject: [PATCH v3 10/13] sata: ahci-da850: add a workaround for controller instability Date: Wed, 18 Jan 2017 14:19:58 +0100 Message-Id: <1484745601-4769-11-git-send-email-bgolaszewski@baylibre.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1484745601-4769-1-git-send-email-bgolaszewski@baylibre.com> References: <1484745601-4769-1-git-send-email-bgolaszewski@baylibre.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org We have a use case with the da850 SATA controller where at PLL0 frequency of 456MHz (needed to properly service the LCD controller) the chip becomes unstable and the hardreset operation is ignored the first time 50% of times. The sata core driver already retries to resume the link because some controllers ignore writes to the SControl register, but just retrying the resume operation doesn't work - we need to issue he phy/wake reset again to make it work. Reimplement ahci_hardreset() in the driver and poke the controller a couple times before really giving up. Signed-off-by: Bartosz Golaszewski --- drivers/ata/ahci_da850.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) -- 2.9.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/ata/ahci_da850.c b/drivers/ata/ahci_da850.c index 11dd87e..0b2b1a4 100644 --- a/drivers/ata/ahci_da850.c +++ b/drivers/ata/ahci_da850.c @@ -16,7 +16,8 @@ #include #include "ahci.h" -#define DRV_NAME "ahci_da850" +#define DRV_NAME "ahci_da850" +#define HARDRESET_RETRIES 5 /* SATA PHY Control Register offset from AHCI base */ #define SATA_P0PHYCR_REG 0x178 @@ -76,6 +77,29 @@ static int ahci_da850_softreset(struct ata_link *link, return ret; } +static int ahci_da850_hardreset(struct ata_link *link, + unsigned int *class, unsigned long deadline) +{ + int ret, retry = HARDRESET_RETRIES; + bool online; + + /* + * In order to correctly service the LCD controller of the da850 SoC, + * we increased the PLL0 frequency to 456MHz from the default 300MHz. + * + * This made the SATA controller unstable and the hardreset operation + * does not always succeed the first time. Before really giving up to + * bring up the link, retry the reset a couple times. + */ + do { + ret = ahci_do_hardreset(link, class, deadline, &online); + if (online) + return ret; + } while (retry--); + + return ret; +} + static struct ata_port_operations ahci_da850_port_ops = { .inherits = &ahci_platform_ops, .softreset = ahci_da850_softreset, @@ -83,6 +107,8 @@ static struct ata_port_operations ahci_da850_port_ops = { * No need to override .pmp_softreset - it's only used for actual * PMP-enabled ports. */ + .hardreset = ahci_da850_hardreset, + .pmp_hardreset = ahci_da850_hardreset, }; static const struct ata_port_info ahci_da850_port_info = {