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[209.132.180.67]) by mx.google.com with ESMTP id f3si33064799plb.206.2016.12.28.18.34.33; Wed, 28 Dec 2016 18:34:33 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752177AbcL2Cec (ORCPT + 7 others); Wed, 28 Dec 2016 21:34:32 -0500 Received: from mail-pg0-f50.google.com ([74.125.83.50]:34763 "EHLO mail-pg0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752137AbcL2Ceb (ORCPT ); Wed, 28 Dec 2016 21:34:31 -0500 Received: by mail-pg0-f50.google.com with SMTP id y62so109510911pgy.1 for ; Wed, 28 Dec 2016 18:34:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aFusvqSYh4Jh7Af6Hi4pHGFYo/P0G3d4jKz3JZ0TrSc=; b=SXLKRb8zWoeCEZhoxy8PsY+IR55TiEJYGFtKLOQofNoVxG+CDA5TCpEg34rLFrCm1B 0SJXNZxflyMOPj80t103Shmak4CW1Tc6HY+ArDXvYXO8PuEH/sZL4isTCa2pyiY9ujxZ fOJe/vtvg2P2bTjO1c3L6uMsSRwy3ttl2iQPA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aFusvqSYh4Jh7Af6Hi4pHGFYo/P0G3d4jKz3JZ0TrSc=; b=ovGKoyLQoRKRIkxWBvahME89swYjyn8QOdXO6aRqoNtVURqOfRYkxpp1egPC1JqPNK QZFkxpMR5gws2zNxnK1kCq81viVNphNmHdVhvTCJt4wtRf1UFoFDR+uf0UB2puL6NH39 /jky7evDLHZR+4NzLCMHNdm3k8DzywPQ4+U4jM8eAW/5H9Kue6yt/oqvqduAH1AobCIk 6CfiPojwoqcQRkCSYfIzM6jX21zA81LTQo4cJnXNBABL7pfeBnxaIpisAXTi2CQG8Jjo n80dBX6kN5jnW0FkSzGgquH4kZZPgPrTGc0nMvcHuX+cR3gFLZWx2xi34EKTE6TiRoDq R+TA== X-Gm-Message-State: AIkVDXJKwjf5JZhO7uqlFDIIkJaCJCEF5p+hV6nxMvskK38nGfXoV7k/rnU4z3Pp+6ftVn6L X-Received: by 10.99.47.7 with SMTP id v7mr74103588pgv.39.1482978871060; Wed, 28 Dec 2016 18:34:31 -0800 (PST) Received: from localhost.localdomain ([104.237.91.229]) by smtp.gmail.com with ESMTPSA id q26sm100055008pfk.94.2016.12.28.18.34.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 28 Dec 2016 18:34:30 -0800 (PST) From: Zhangfei Gao To: Stephen Boyd , Rob Herring , Arnd Bergmann , haojian.zhuang@linaro.org, guodong Xu Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Zhangfei Gao Subject: [PATCH v2 1/2] dt-bindings: Document the hi3660 clock bindings Date: Thu, 29 Dec 2016 10:33:24 +0800 Message-Id: <1482978805-6981-2-git-send-email-zhangfei.gao@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1482978805-6981-1-git-send-email-zhangfei.gao@linaro.org> References: <1482978805-6981-1-git-send-email-zhangfei.gao@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT bindings documentation for hi3660 SoC clock. Signed-off-by: Zhangfei Gao --- .../devicetree/bindings/clock/hi3660-clock.txt | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/hi3660-clock.txt -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/clock/hi3660-clock.txt b/Documentation/devicetree/bindings/clock/hi3660-clock.txt new file mode 100644 index 0000000..cc9b86c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/hi3660-clock.txt @@ -0,0 +1,42 @@ +* Hisilicon Hi3660 Clock Controller + +The Hi3660 clock controller generates and supplies clock to various +controllers within the Hi3660 SoC. + +Required Properties: + +- compatible: the compatible should be one of the following strings to + indicate the clock controller functionality. + + - "hisilicon,hi3660-crgctrl" + - "hisilicon,hi3660-pctrl" + - "hisilicon,hi3660-pmuctrl" + - "hisilicon,hi3660-sctrl" + - "hisilicon,hi3660-iomcu" + +- reg: physical base address of the controller and length of memory mapped + region. + +- #clock-cells: should be 1. + +Each clock is assigned an identifier and client nodes use this identifier +to specify the clock which they consume. + +All these identifier could be found in . + +Examples: + crg_ctrl: clock-controller@fff35000 { + compatible = "hisilicon,hi3660-crgctrl", "syscon"; + reg = <0x0 0xfff35000 0x0 0x1000>; + #clock-cells = <1>; + }; + + uart0: serial@fdf02000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf02000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, + <&crg_ctrl HI3660_PCLK>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + };