From patchwork Tue Dec 13 10:09:19 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 87819 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp2118365qgi; Tue, 13 Dec 2016 02:09:59 -0800 (PST) X-Received: by 10.99.131.67 with SMTP id h64mr173120153pge.135.1481623798913; Tue, 13 Dec 2016 02:09:58 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v142si47446441pgb.7.2016.12.13.02.09.58; Tue, 13 Dec 2016 02:09:58 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@baylibre-com.20150623.gappssmtp.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932901AbcLMKJm (ORCPT + 7 others); Tue, 13 Dec 2016 05:09:42 -0500 Received: from mail-wj0-f173.google.com ([209.85.210.173]:33390 "EHLO mail-wj0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932823AbcLMKJi (ORCPT ); Tue, 13 Dec 2016 05:09:38 -0500 Received: by mail-wj0-f173.google.com with SMTP id xy5so95851319wjc.0 for ; Tue, 13 Dec 2016 02:09:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SKBcHtbJQJ7cPM7qRt2XEaoq2qJcb1GLqDRHrbvkAac=; b=VlzARh7RbXYKwgv/8IAyB+G1Jb2rsedJj7sO7VQwSaz73mukb5xdXgZLkYEKVvkaLj +ouEHIbEl4/oKIAiPh/DZJ22lQvw/sshDvxC5XCV/yqAta9gOkrsUrMF7+w2iw8xBcZ6 DHrjnsqNOzRIEc7ZSU1XIt3T8889a09RfCpB6FDMyYNsFtuDrMVP7xoMz5yxDpoGFojg m4UZDnNJEd6K+Iwq4InuElaCj5zFUpUlwrWyYmQJLOfb9FE90Qq+ExytzBikeoJ8F4+H DrzAB5J6LwVRc5ELZMwj4m8OjovS8Jp7o6uZZt//DcO2PaTDzg6yyMsfo6Fv532zevqJ BJcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SKBcHtbJQJ7cPM7qRt2XEaoq2qJcb1GLqDRHrbvkAac=; b=T27z8d+dShu492fz6zgNR7UWe5mVssMijJC6cCdU11FkFT2gb1YB7b6dad6DYNRAlw T9t5rT2KMolgDIwnjS7B36KP3srvuCrd4Mdfi7TUdms0cuAtxvKgo1V2bkm/K/6Hjn4e w0Si3SqJc7zwmrHevFXhRe+iNg8tvBUJFmKk7Oqjfzx9DK09HHgLDPp1+p3mOLBt8FE3 agRNCgBKt5MWy6vL0A3vHLt9+XBtLICuWvInbbj/LNbykjBU73qtJPZsU3c77b3Fh8Mu Zr9Fd6PBasFTP0LXTnH8dMQRnLVSoACZFR9Nyn8H0bWh7sza9sBnpquZW1nZn4ISSlUX P6KA== X-Gm-Message-State: AKaTC035ATxdFXB99DoywkrbE9bQGElIhQCaPn7wiSQOgJEzTlgoRcDJx/D4Gbk7iDCNKVUo X-Received: by 10.194.109.65 with SMTP id hq1mr56466458wjb.37.1481623776673; Tue, 13 Dec 2016 02:09:36 -0800 (PST) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id 138sm1808513wms.20.2016.12.13.02.09.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 13 Dec 2016 02:09:36 -0800 (PST) From: Bartosz Golaszewski To: Jyri Sarha , Tomi Valkeinen , David Airlie , Kevin Hilman , Michael Turquette , Sekhar Nori , Rob Herring , Frank Rowand , Mark Rutland , Laurent Pinchart , Peter Ujfalusi , Russell King , Maxime Ripard Cc: LKML , arm-soc , linux-drm , linux-devicetree , Bartosz Golaszewski Subject: [PATCH v7 5/5] ARM: dts: da850: specify the maximum pixel clock rate for tilcdc Date: Tue, 13 Dec 2016 11:09:19 +0100 Message-Id: <1481623759-12786-6-git-send-email-bgolaszewski@baylibre.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1481623759-12786-1-git-send-email-bgolaszewski@baylibre.com> References: <1481623759-12786-1-git-send-email-bgolaszewski@baylibre.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org At maximum CPU frequency of 300 MHz the maximum pixel clock frequency is 37.5 MHz[1]. We must filter out any mode for which the calculated pixel clock rate would exceed this value. Specify the max-pixelclock property for the display node for da850-lcdk. [1] http://processors.wiki.ti.com/index.php/OMAP-L1x/C674x/AM1x_LCD_Controller_(LCDC)_Throughput_and_Optimization_Techniques Signed-off-by: Bartosz Golaszewski --- arch/arm/boot/dts/da850.dtsi | 1 + 1 file changed, 1 insertion(+) -- 2.9.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index 6b0ef3d..58b1566 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -462,6 +462,7 @@ compatible = "ti,da850-tilcdc"; reg = <0x213000 0x1000>; interrupts = <52>; + max-pixelclock = <37500>; status = "disabled"; }; };