From patchwork Wed Nov 23 08:07:55 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhangfei Gao X-Patchwork-Id: 83562 Delivered-To: patch@linaro.org Received: by 10.140.97.165 with SMTP id m34csp2513369qge; Wed, 23 Nov 2016 00:10:30 -0800 (PST) X-Received: by 10.99.105.70 with SMTP id e67mr3064069pgc.99.1479888630591; Wed, 23 Nov 2016 00:10:30 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m16si23051332pgn.140.2016.11.23.00.10.30; Wed, 23 Nov 2016 00:10:30 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932853AbcKWIK2 (ORCPT + 7 others); Wed, 23 Nov 2016 03:10:28 -0500 Received: from mail-pg0-f42.google.com ([74.125.83.42]:34889 "EHLO mail-pg0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932865AbcKWIK1 (ORCPT ); Wed, 23 Nov 2016 03:10:27 -0500 Received: by mail-pg0-f42.google.com with SMTP id p66so3465280pga.2 for ; Wed, 23 Nov 2016 00:09:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iMSbsmSlRvxDEwWdJ0jved8vF7k9QSaxW3IPHWmu8oA=; b=AO/Yd9JpVqQu4zA/+DhwJFiakL177KGgcFrZDfqdnJztRrAeBqvqIzD2IG0sDn6dHK 3pcdtCk/5SXFaDHW2Flc4vded9h5Dx02tPnRMeY+RF2OoFNQXRdds8VCDdMEMnbRRuT7 Ey+UhjO441X+5yHIZEHUMfXxhSC3jMXfeDC30= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iMSbsmSlRvxDEwWdJ0jved8vF7k9QSaxW3IPHWmu8oA=; b=hTHNj2qv8erZDRjAao7EGllShX39zhj34rS7lWcunWmCDAASQ7ZkWYWzeymxLg0nQ8 xP9gffz7JhZCQSCsBQNEP5hrOAlG2Ec1CLuoFTgGwPy91KBZ/+BSnQIH7IbGMF+JMjbt eAFL96feu+vIa2qrEloB/ujQHpjeAY6bPTz4rOltbcxDE3Ep1c+nGxeeF3dgrq5jMS2B clTFMgzOj+pGAQGJVdDjIHmS8Z4MGlM5OfL9bil+EuFOVQV8HCLS/WhxfPHuAW2/ZdD3 FRRLqRpyWNUP36vo8KRDhys6TpkPpPc2UbTYX8kHEmnY2wy1Fj7tucsby8THLFGkFrFd KsWg== X-Gm-Message-State: AKaTC01eaUBpsAxQyh6ckHlnv+62fPGy2XgbDZ6ugdakvwjesXUZGUu3rKnxut7ib21Oqc9G X-Received: by 10.98.194.130 with SMTP id w2mr1670666pfk.143.1479888558117; Wed, 23 Nov 2016 00:09:18 -0800 (PST) Received: from localhost.localdomain ([104.237.91.22]) by smtp.gmail.com with ESMTPSA id s8sm50422542pfj.45.2016.11.23.00.09.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 23 Nov 2016 00:09:17 -0800 (PST) From: Zhangfei Gao To: Philipp Zabel Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Zhangfei Gao Subject: [RFC v2: PATCH 1/2] dt-bindings: Document the hi3660 reset bindings Date: Wed, 23 Nov 2016 16:07:55 +0800 Message-Id: <1479888476-13138-2-git-send-email-zhangfei.gao@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1479888476-13138-1-git-send-email-zhangfei.gao@linaro.org> References: ,> <1479888476-13138-1-git-send-email-zhangfei.gao@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT bindings documentation for hi3660 SoC reset controller. Signed-off-by: Zhangfei Gao --- .../bindings/reset/hisilicon,hi3660-reset.txt | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt new file mode 100644 index 0000000..250daf2 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt @@ -0,0 +1,51 @@ +Hisilicon System Reset Controller +====================================== + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +The reset controller registers are part of the system-ctl block on +hi3660 SoC. + +Required properties: +- compatible: should be + "hisilicon,hi3660-reset" +- #reset-cells: 1, see below +- hisi,rst-syscon: phandle of the reset's syscon. +- hisi,reset-bits: Contains the reset control register information + Should contain 2 cells for each reset exposed to + consumers, defined as: + Cell #1 : offset from the syscon register base + Cell #2 : bits position of the control register + +Example: + iomcu: iomcu@ffd7e000 { + compatible = "hisilicon,hi3660-iomcu", "syscon"; + reg = <0x0 0xffd7e000 0x0 0x1000>; + }; + + iomcu_rst: iomcu_rst_controller { + compatible = "hisilicon,hi3660-reset"; + #reset-cells = <1>; + hisi,rst-syscon = <&iomcu>; + hisi,reset-bits = <0x20 0x8 /* 0: i2c0 */ + 0x20 0x10 /* 1: i2c1 */ + 0x20 0x20 /* 2: i2c2 */ + 0x20 0x8000000>; /* 3: i2c6 */ + }; + +Specifying reset lines connected to IP modules +============================================== +example: + + i2c0: i2c@..... { + ... + resets = <&iomcu_rst 0>; + ... + }; + + i2c1: i2c@..... { + ... + resets = <&iomcu_rst 1>; + ... + };