From patchwork Thu Oct 20 04:44:06 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 78400 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp593443qge; Wed, 19 Oct 2016 21:44:04 -0700 (PDT) X-Received: by 10.98.58.73 with SMTP id h70mr17715851pfa.138.1476938644207; Wed, 19 Oct 2016 21:44:04 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s17si36733656pgi.151.2016.10.19.21.44.03; Wed, 19 Oct 2016 21:44:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754087AbcJTEoB (ORCPT + 7 others); Thu, 20 Oct 2016 00:44:01 -0400 Received: from conuserg-07.nifty.com ([210.131.2.74]:21548 "EHLO conuserg-07.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753111AbcJTEoA (ORCPT ); Thu, 20 Oct 2016 00:44:00 -0400 Received: from beagle.diag.org (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-07.nifty.com with ESMTP id u9K4fao3020258; Thu, 20 Oct 2016 13:41:36 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com u9K4fao3020258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1476938497; bh=B9f4JTEY7e6S8GFbQ1AMKfd4PByl/prrAQXuZVz7TDc=; h=From:To:Cc:Subject:Date:From; b=DAZHZB4q0ifiRnAUlJ+DCPCG7oFwuNE1d3PIFUlcdIMEOK4jsuOa3yS8gZOM0fq26 4d1vcEFeLmWTFyPHt7l3GLyc6rqJJFG50RfUY1kRf21ZbCtr4PD/knwPCWT+jBJw4C DLn7BZmPxlZSiEmgqFohNw3HsSTl5fZgsEuYBCI7Qhlv6hVdVunjqU6OIN77F+1cy0 okwNL3tBNYmJLAF1kY37/H9sMPoM48FAX4vGKnhMUc2aDLeKrCXNN2AlaUu8rvJmUM tb92x2rdCC/kdbiDWAcHpDKbVmJRXt/WxRf/CRxZVYlpf2SJdh3JTW3bCy7LvFmEcd lWOdewWWrsm6A== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-arm-kernel@lists.infradead.org Cc: Viresh Kumar , Masahiro Yamada , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Will Deacon , Mark Rutland , Catalin Marinas Subject: [PATCH v3 1/2] arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC Date: Thu, 20 Oct 2016 13:44:06 +0900 Message-Id: <1476938647-26376-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a CPU clock to every CPU node and a CPU OPP table to use the generic cpufreq driver. Note: clock-latency-ns (300ns) was calculated based on the CPU-gear switch sequencer spec; it takes 12 clock cycles on the sequencer running at 50 MHz, plus a bit additional latency. Signed-off-by: Masahiro Yamada --- Changes in v2: - Match the node name to the opp-hz property. arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 38 ++++++++++++++++++++++++ 1 file changed, 38 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Viresh Kumar diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi index 73e0acf..bb05f0a 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -70,14 +70,18 @@ device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x000>; + clocks = <&sys_clk 33>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x001>; + clocks = <&sys_clk 33>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; }; }; @@ -86,6 +90,40 @@ method = "smc"; }; + cluster0_opp: opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp@245000000 { + opp-hz = /bits/ 64 <245000000>; + clock-latency-ns = <300>; + }; + opp@250000000 { + opp-hz = /bits/ 64 <250000000>; + clock-latency-ns = <300>; + }; + opp@490000000 { + opp-hz = /bits/ 64 <490000000>; + clock-latency-ns = <300>; + }; + opp@500000000 { + opp-hz = /bits/ 64 <500000000>; + clock-latency-ns = <300>; + }; + opp@653334000 { + opp-hz = /bits/ 64 <653334000>; + clock-latency-ns = <300>; + }; + opp@666667000 { + opp-hz = /bits/ 64 <666667000>; + clock-latency-ns = <300>; + }; + opp@980000000 { + opp-hz = /bits/ 64 <980000000>; + clock-latency-ns = <300>; + }; + }; + clocks { refclk: ref { compatible = "fixed-clock";