From patchwork Sun Oct 16 14:59:17 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 77695 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp11463qge; Sun, 16 Oct 2016 08:00:55 -0700 (PDT) X-Received: by 10.67.3.74 with SMTP id bu10mr26497034pad.16.1476630055549; Sun, 16 Oct 2016 08:00:55 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q126si23397987pga.81.2016.10.16.08.00.55; Sun, 16 Oct 2016 08:00:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756634AbcJPPAo (ORCPT + 7 others); Sun, 16 Oct 2016 11:00:44 -0400 Received: from conuserg-12.nifty.com ([210.131.2.79]:25213 "EHLO conuserg-12.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756546AbcJPPAi (ORCPT ); Sun, 16 Oct 2016 11:00:38 -0400 Received: from grover.sesame (FL1-111-169-71-157.osk.mesh.ad.jp [111.169.71.157]) (authenticated) by conuserg-12.nifty.com with ESMTP id u9GExPp7010750; Sun, 16 Oct 2016 23:59:33 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-12.nifty.com u9GExPp7010750 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1476629975; bh=GKlO0OhbVipdUwBXgfgYxQ1lIxTA6i2KWawDQbLI/z8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=wQVpn+X+BcrWwo2aE+OissvJfTMS7Yi1UjkVDgpL6+lR039lBVM5F2ZhI37Vgd6Dm DvA9u+L9O1c0tz3tpaQMAz4q/UX7nF2T2roYLD2A0+guk+MJvO7Egof9tgppDir1lN JZenmVVBjrU7V7FJu3Gmapm92G8HnEwi2z3YsjXUcXCx6x2k//81m7LToiHAJCTe9z oN2vk4jIV9JObKXrxjcX4A9HATs659crnDKBY8zwBzstxfVM4nyorZXjLNz5hLDTtx Zr6M4z1i5tyJQQdxVZBVCM/5Gfq9AtPW5n1z1DaVU6IH2ud1mf0wsUoiEMkcot8W0Q fh1mkqrJjCB0g== X-Nifty-SrcIP: [111.169.71.157] From: Masahiro Yamada To: linux-arm-kernel@lists.infradead.org Cc: Viresh Kumar , Masahiro Yamada , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Will Deacon , Mark Rutland , Catalin Marinas Subject: [PATCH 2/3] arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC Date: Sun, 16 Oct 2016 23:59:17 +0900 Message-Id: <1476629958-25368-3-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1476629958-25368-1-git-send-email-yamada.masahiro@socionext.com> References: <1476629958-25368-1-git-send-email-yamada.masahiro@socionext.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a CPU clock to every CPU node and a CPU OPP table to use the generic cpufreq driver. Note: clock-latency-ns (300ns) was calculated based on the CPU-gear switch sequencer spec; it takes 12 clock cycles on the sequencer running at 50 MHz, plus a bit additional latency. Signed-off-by: Masahiro Yamada --- arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 38 ++++++++++++++++++++++++ 1 file changed, 38 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi index 73e0acf..e3eb10f 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -70,14 +70,18 @@ device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x000>; + clocks = <&sys_clk 33>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x001>; + clocks = <&sys_clk 33>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; }; }; @@ -86,6 +90,40 @@ method = "smc"; }; + cluster0_opp: opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp@245000000 { + opp-hz = /bits/ 64 <245000000>; + clock-latency-ns = <300>; + }; + opp@250000000 { + opp-hz = /bits/ 64 <250000000>; + clock-latency-ns = <300>; + }; + opp@490000000 { + opp-hz = /bits/ 64 <490000000>; + clock-latency-ns = <300>; + }; + opp@500000000 { + opp-hz = /bits/ 64 <500000000>; + clock-latency-ns = <300>; + }; + opp@653333333 { + opp-hz = /bits/ 64 <653334000>; + clock-latency-ns = <300>; + }; + opp@666666666 { + opp-hz = /bits/ 64 <666667000>; + clock-latency-ns = <300>; + }; + opp@980000000 { + opp-hz = /bits/ 64 <980000000>; + clock-latency-ns = <300>; + }; + }; + clocks { refclk: ref { compatible = "fixed-clock";