From patchwork Wed Sep 14 05:11:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 76129 Delivered-To: patch@linaro.org Received: by 10.140.106.72 with SMTP id d66csp1692909qgf; Tue, 13 Sep 2016 22:13:33 -0700 (PDT) X-Received: by 10.98.51.131 with SMTP id z125mr1096468pfz.109.1473830012673; Tue, 13 Sep 2016 22:13:32 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h132si31526237pfe.115.2016.09.13.22.13.32; Tue, 13 Sep 2016 22:13:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755568AbcINFNa (ORCPT + 7 others); Wed, 14 Sep 2016 01:13:30 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:57332 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754710AbcINFN1 (ORCPT ); Wed, 14 Sep 2016 01:13:27 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id u8E5CZt2007570; Wed, 14 Sep 2016 00:12:35 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id u8E5CYoW031378; Wed, 14 Sep 2016 00:12:34 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Wed, 14 Sep 2016 00:12:34 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id u8E5CHvI003576; Wed, 14 Sep 2016 00:12:29 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Arnd Bergmann , Jingoo Han , , , , , Pratyush Anand CC: , , , , , , Joao Pinto , Rob Herring , , Subject: [RFC PATCH 02/11] pci: endpoint: introduce configfs entry for configuring EP functions Date: Wed, 14 Sep 2016 10:41:58 +0530 Message-ID: <1473829927-20466-3-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1473829927-20466-1-git-send-email-kishon@ti.com> References: <1473829927-20466-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Introduce a new configfs entry to configure the EP function (like configuring the standard configuration header entries) and to bind the function with a controller. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/endpoint/Kconfig | 4 +- drivers/pci/endpoint/Makefile | 3 +- drivers/pci/endpoint/pci-ep-cfs.c | 275 +++++++++++++++++++++++++++++++++++++ 3 files changed, 280 insertions(+), 2 deletions(-) create mode 100644 drivers/pci/endpoint/pci-ep-cfs.c -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pci/endpoint/Kconfig b/drivers/pci/endpoint/Kconfig index a6d827c..f1dd206 100644 --- a/drivers/pci/endpoint/Kconfig +++ b/drivers/pci/endpoint/Kconfig @@ -13,7 +13,9 @@ config PCI_ENDPOINT Enabling this option will build the endpoint library, which includes endpoint controller library and endpoint function - library. + library. This will also enable the configfs entry required to + configure the endpoint function and used to bind the + function with a endpoint controller. If in doubt, say "N" to disable Endpoint support. diff --git a/drivers/pci/endpoint/Makefile b/drivers/pci/endpoint/Makefile index dbc5517..67c88bf 100644 --- a/drivers/pci/endpoint/Makefile +++ b/drivers/pci/endpoint/Makefile @@ -2,4 +2,5 @@ # Makefile for PCI Endpoint Support # -obj-$(CONFIG_PCI_ENDPOINT) := pci-epc-core.o pci-epf-core.o +obj-$(CONFIG_PCI_ENDPOINT) := pci-epc-core.o pci-epf-core.o \ + pci-ep-cfs.o diff --git a/drivers/pci/endpoint/pci-ep-cfs.c b/drivers/pci/endpoint/pci-ep-cfs.c new file mode 100644 index 0000000..d11ae34 --- /dev/null +++ b/drivers/pci/endpoint/pci-ep-cfs.c @@ -0,0 +1,275 @@ +/** + * pci-ep-cfs.c - configfs to configure the PCI endpoint + * + * Copyright (C) 2016 Texas Instruments + * Author: Kishon Vijay Abraham I + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 of + * the License as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include + +#include +#include + +struct pci_epf_info { + struct config_item pci_epf; + struct pci_epf *epf; +}; + +static inline struct pci_epf_info *to_pci_epf_info(struct config_item *item) +{ + return container_of(item, struct pci_epf_info, pci_epf); +} + +#define PCI_EPF_HEADER_R(_name) \ +static ssize_t pci_epf_##_name##_show(struct config_item *item, \ + char *page) \ +{ \ + return sprintf(page, "0x%04x\n", \ + to_pci_epf_info(item)->epf->header->_name); \ +} + +#define PCI_EPF_HEADER_W_u32(_name) \ +static ssize_t pci_epf_##_name##_store(struct config_item *item, \ + const char *page, size_t len) \ +{ \ + u32 val; \ + int ret; \ + ret = kstrtou32(page, 0, &val); \ + if (ret) \ + return ret; \ + to_pci_epf_info(item)->epf->header->_name = val; \ + return len; \ +} + +#define PCI_EPF_HEADER_W_u16(_name) \ +static ssize_t pci_epf_##_name##_store(struct config_item *item, \ + const char *page, size_t len) \ +{ \ + u16 val; \ + int ret; \ + ret = kstrtou16(page, 0, &val); \ + if (ret) \ + return ret; \ + to_pci_epf_info(item)->epf->header->_name = val; \ + return len; \ +} + +#define PCI_EPF_HEADER_W_u8(_name) \ +static ssize_t pci_epf_##_name##_store(struct config_item *item, \ + const char *page, size_t len) \ +{ \ + u8 val; \ + int ret; \ + ret = kstrtou8(page, 0, &val); \ + if (ret) \ + return ret; \ + to_pci_epf_info(item)->epf->header->_name = val; \ + return len; \ +} + +#define PCI_EPF_HEADER_RW(_name, _type) \ + PCI_EPF_HEADER_R(_name) \ + PCI_EPF_HEADER_W_##_type(_name) + +static ssize_t pci_epf_peripheral_store(struct config_item *item, + const char *page, size_t len) +{ + struct pci_epf_info *epf_info = to_pci_epf_info(item); + char *dev_name; + + dev_name = kstrdup(page, GFP_KERNEL); + if (!dev_name) + return -ENOMEM; + if (dev_name[len - 1] == '\n') + dev_name[len - 1] = '\0'; + + epf_info->epf->hw_devname = dev_name; + return len; +} + +static ssize_t pci_epf_peripheral_show(struct config_item *item, + char *page) +{ + return sprintf(page, "%s\n", + to_pci_epf_info(item)->epf->hw_devname); +} + +static ssize_t pci_epf_function_show(struct config_item *item, + char *page) +{ + return sprintf(page, "%s\n", + to_pci_epf_info(item)->epf->name); +} + +static ssize_t pci_epf_epc_store(struct config_item *item, + const char *page, size_t len) +{ + int ret; + struct pci_epf_info *epf_info = to_pci_epf_info(item); + char *epc_name; + + epc_name = kstrdup(page, GFP_KERNEL); + if (!epc_name) + return -ENOMEM; + if (epc_name[len - 1] == '\n') + epc_name[len - 1] = '\0'; + + if (epf_info->epf->epc) + pci_epc_unbind_epf(epf_info->epf); + + epf_info->epf->pci_epc_name = epc_name; + ret = pci_epc_bind_epf(epf_info->epf); + if (ret) + return -EINVAL; + + return len; +} + +static ssize_t pci_epf_epc_show(struct config_item *item, + char *page) +{ + return sprintf(page, "%s\n", + to_pci_epf_info(item)->epf->pci_epc_name); +} + +PCI_EPF_HEADER_RW(vendorid, u16); +PCI_EPF_HEADER_RW(deviceid, u16); +PCI_EPF_HEADER_RW(revid, u16); +PCI_EPF_HEADER_RW(progif_code, u16); +PCI_EPF_HEADER_RW(subclass_code, u16); +PCI_EPF_HEADER_RW(baseclass_code, u16); +PCI_EPF_HEADER_RW(cache_line_size, u16); +PCI_EPF_HEADER_RW(subsys_vendor_id, u16); +PCI_EPF_HEADER_RW(subsys_id, u16); +PCI_EPF_HEADER_RW(interrupt_pin, u16); + +CONFIGFS_ATTR(pci_epf_, vendorid); +CONFIGFS_ATTR(pci_epf_, deviceid); +CONFIGFS_ATTR(pci_epf_, revid); +CONFIGFS_ATTR(pci_epf_, progif_code); +CONFIGFS_ATTR(pci_epf_, subclass_code); +CONFIGFS_ATTR(pci_epf_, baseclass_code); +CONFIGFS_ATTR(pci_epf_, cache_line_size); +CONFIGFS_ATTR(pci_epf_, subsys_vendor_id); +CONFIGFS_ATTR(pci_epf_, subsys_id); +CONFIGFS_ATTR(pci_epf_, interrupt_pin); +CONFIGFS_ATTR(pci_epf_, peripheral); +CONFIGFS_ATTR_RO(pci_epf_, function); +CONFIGFS_ATTR(pci_epf_, epc); + +static struct configfs_attribute *pci_epf_attrs[] = { + &pci_epf_attr_vendorid, + &pci_epf_attr_deviceid, + &pci_epf_attr_revid, + &pci_epf_attr_progif_code, + &pci_epf_attr_subclass_code, + &pci_epf_attr_baseclass_code, + &pci_epf_attr_cache_line_size, + &pci_epf_attr_subsys_vendor_id, + &pci_epf_attr_subsys_id, + &pci_epf_attr_interrupt_pin, + &pci_epf_attr_peripheral, + &pci_epf_attr_function, + &pci_epf_attr_epc, + NULL, +}; + +static void pci_epf_release(struct config_item *item) +{ + struct pci_epf_info *epf_info = to_pci_epf_info(item); + + pci_epf_destroy(epf_info->epf); + kfree(epf_info); +} + +static struct configfs_item_operations pci_epf_ops = { + .release = pci_epf_release, +}; + +static struct config_item_type pci_epf_type = { + .ct_item_ops = &pci_epf_ops, + .ct_attrs = pci_epf_attrs, + .ct_owner = THIS_MODULE, +}; + +static struct config_item *pci_epf_make(struct config_group *group, + const char *name) +{ + struct pci_epf_info *epf_info; + struct pci_epf *epf; + + epf_info = kzalloc(sizeof(*epf_info), GFP_KERNEL); + if (!epf_info) + return ERR_PTR(-ENOMEM); + + epf = pci_epf_create(name); + if (IS_ERR(epf)) { + pr_err("failed to create endpoint function device\n"); + return ERR_PTR(-EINVAL); + } + + epf_info->epf = epf; + + config_item_init_type_name(&epf_info->pci_epf, name, + &pci_epf_type); + + return &epf_info->pci_epf; +} + +static struct configfs_group_operations pci_ep_ops = { + .make_item = pci_epf_make, +}; + +static struct config_item_type pci_ep_type = { + .ct_group_ops = &pci_ep_ops, + .ct_owner = THIS_MODULE, +}; + +static struct configfs_subsystem pci_ep_cfs_subsys = { + .su_group = { + .cg_item = { + .ci_namebuf = "pci_ep", + .ci_type = &pci_ep_type, + }, + }, + .su_mutex = __MUTEX_INITIALIZER(pci_ep_cfs_subsys.su_mutex), +}; + +static int __init pci_ep_cfs_init(void) +{ + int ret; + + config_group_init(&pci_ep_cfs_subsys.su_group); + + ret = configfs_register_subsystem(&pci_ep_cfs_subsys); + if (ret) + pr_err("Error %d while registering subsystem %s\n", + ret, pci_ep_cfs_subsys.su_group.cg_item.ci_namebuf); + + return ret; +} +module_init(pci_ep_cfs_init); + +static void __exit pci_ep_cfs_exit(void) +{ + configfs_unregister_subsystem(&pci_ep_cfs_subsys); +} +module_exit(pci_ep_cfs_exit); + +MODULE_DESCRIPTION("PCI EP CONFIGFS"); +MODULE_AUTHOR("Kishon Vijay Abraham I "); +MODULE_LICENSE("GPL v2");