From patchwork Tue Sep 13 17:10:53 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 76095 Delivered-To: patch@linaro.org Received: by 10.140.106.72 with SMTP id d66csp1465200qgf; Tue, 13 Sep 2016 10:13:15 -0700 (PDT) X-Received: by 10.66.120.143 with SMTP id lc15mr3062822pab.139.1473786795598; Tue, 13 Sep 2016 10:13:15 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d68si28394392pfa.77.2016.09.13.10.13.15; Tue, 13 Sep 2016 10:13:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759777AbcIMRNG (ORCPT + 7 others); Tue, 13 Sep 2016 13:13:06 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:53259 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759805AbcIMRM7 (ORCPT ); Tue, 13 Sep 2016 13:12:59 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id u8DHC2QP012875; Tue, 13 Sep 2016 12:12:02 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id u8DHC1fe017121; Tue, 13 Sep 2016 12:12:01 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Tue, 13 Sep 2016 12:12:00 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id u8DHAuX0013681; Tue, 13 Sep 2016 12:11:56 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Arnd Bergmann , Jingoo Han , , , , , Pratyush Anand CC: , , , , , , Joao Pinto , Rob Herring , , Subject: [RFC PATCH] HACK: pci: controller: dra7xx: disable smart idle Date: Tue, 13 Sep 2016 22:40:53 +0530 Message-ID: <1473786653-12759-12-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1473786653-12759-1-git-send-email-kishon@ti.com> References: <1473786653-12759-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Smart idle prevents RC to access the memory space of this controller. Set the idle mode to smart idle wakeup. This should ideally be done in hwmod. Till it's figured out how to configure it in hwmod, mark this as HACK. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/pci-dra7xx.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pci/controller/pci-dra7xx.c b/drivers/pci/controller/pci-dra7xx.c index 5b49367..31211e6 100644 --- a/drivers/pci/controller/pci-dra7xx.c +++ b/drivers/pci/controller/pci-dra7xx.c @@ -30,6 +30,14 @@ /* PCIe controller wrapper DRA7XX configuration registers */ +#define PCIECTRL_DRA7XX_CONF_SYSCONFIG 0x0010 +#define SIDLE_MASK 3 +#define SIDLE_SHIFT 2 +#define SIDLE_FORCE 0x0 +#define SIDLE_NO 0x1 +#define SIDLE_SMART 0x2 +#define SIDLE_SMART_WKUP 0x3 + #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN 0x0024 #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN 0x0028 #define ERR_SYS BIT(0) @@ -606,6 +614,10 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) goto err_gpio; break; case DW_PCIE_EP_TYPE: + reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_SYSCONFIG); + reg &= ~(SIDLE_MASK << SIDLE_SHIFT); + reg |= SIDLE_SMART_WKUP << SIDLE_SHIFT; + dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_SYSCONFIG, reg); dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE, DEVICE_TYPE_EP); ret = dra7xx_add_pcie_ep(dra7xx, pdev);