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([80.12.42.230]) by smtp.gmail.com with ESMTPSA id db6sm42619757wjb.2.2016.06.16.02.21.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 16 Jun 2016 02:21:23 -0700 (PDT) From: Gabriel Fernandez To: Rob Herring , Mark Rutland , Ian Campbell , Kumar Gala , Srinivas Kandagatla , Maxime Coquelin , Patrice Chotard , Russell King , Michael Turquette , Stephen Boyd , Olivier Bideau , Gabriel Fernandez , Geert Uytterhoeven , Sebastian Hesselbarth , Andrzej Hajda , Pankaj Dev , Dinh Nguyen , Arnd Bergmann , Thierry Reding Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@stlinux.com, linux-clk@vger.kernel.org, Lee Jones , Peter Griffin , , , , Subject: [RESEND PATCH v2 13/13] ARM: DT: STi: STiH410: clock configuration to address 720p and 1080p Date: Thu, 16 Jun 2016 11:20:33 +0200 Message-Id: <1466068833-5055-14-git-send-email-gabriel.fernandez@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1466068833-5055-1-git-send-email-gabriel.fernandez@linaro.org> References: <1466068833-5055-1-git-send-email-gabriel.fernandez@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org It is necessary to properly configure these clocks in order to address 720p and 1080p HDMI resolution. Signed-off-by: Vincent Abriou Signed-off-by: Gabriel Fernandez --- arch/arm/boot/dts/stih410.dtsi | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi index 18ed1ad..7eec729 100644 --- a/arch/arm/boot/dts/stih410.dtsi +++ b/arch/arm/boot/dts/stih410.dtsi @@ -103,7 +103,10 @@ #size-cells = <1>; assigned-clocks = <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_flexgen CLK_COMPO_DVP>, + <&clk_s_c0_flexgen CLK_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, <&clk_s_d2_flexgen CLK_PIX_GDP1>, @@ -113,14 +116,21 @@ assigned-clock-parents = <0>, <0>, + <0>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_pll1 0>, <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>; - assigned-clock-rates = <297000000>, <297000000>; + assigned-clock-rates = <297000000>, + <108000000>, + <0>, + <400000000>, + <400000000>; ranges;