From patchwork Mon Apr 25 23:08:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Gross X-Patchwork-Id: 66650 Delivered-To: patch@linaro.org Received: by 10.140.93.198 with SMTP id d64csp1300477qge; Mon, 25 Apr 2016 16:10:02 -0700 (PDT) X-Received: by 10.98.80.206 with SMTP id g75mr626367pfj.127.1461625802255; Mon, 25 Apr 2016 16:10:02 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f18si581435pfd.206.2016.04.25.16.10.02; Mon, 25 Apr 2016 16:10:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752016AbcDYXJ7 (ORCPT + 7 others); Mon, 25 Apr 2016 19:09:59 -0400 Received: from mail-oi0-f48.google.com ([209.85.218.48]:34436 "EHLO mail-oi0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752249AbcDYXJD (ORCPT ); Mon, 25 Apr 2016 19:09:03 -0400 Received: by mail-oi0-f48.google.com with SMTP id k142so193291871oib.1 for ; Mon, 25 Apr 2016 16:09:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZSZAHFtIbvhq3wKatbuJPaUnHDOhhWZY+MPojE6z+Ew=; b=fl4/s+yacONaPp9T2Z7pHqMQ/gbj3d8/ubdAEAlMcySy/QoZRpOLiCbTAn8zSzzXH1 Fc9scidM87uIgHm4g1aHMTp7fsmwObG6Bfy8jYhtKRtvicgMzaacPKZtI5baDDkJ+gMD JSFRKe4TgSVZoiBxrKeu6FjTr/d/tEsViZdAc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZSZAHFtIbvhq3wKatbuJPaUnHDOhhWZY+MPojE6z+Ew=; b=CwCYwANfWzzmTPg3/Ax2J17cjx4kFjyqCBLYoqYY2WttZgWhKYMZ24iiLJeC9lrt81 BZO5n2HFTwTwMDxEiuk/M8pKORW0sEJejtc3Kp4LBHFRGql3SyzHSp0DBvLwo5vXlx0P tKV8Pwm9FuEBdnpeoh5EUZMVPo8cNIJeR5L7Bzq68pDnlO3cutAeJyUMcuZjriCXYj1N 9g8ffxchWBhH+9XasOozO/5V4IARjIdFtEx24b7LK9XKE8fs83GV39ML4uWi/3HyBZcV 6pyJQXJFShsaqBmZWvLXo+zBlb+Xz7UUuTasvJFgeZVAgpp7WS4x60I2EPcngqhdaJkL AMqg== X-Gm-Message-State: AOPr4FVYCshbMFYbgaGVZYwsgGY7fxJTlERCtVW2ZpiNybt3uCQM2GdyWb2nWHln5a926cZL X-Received: by 10.202.203.14 with SMTP id b14mr15577459oig.56.1461625741538; Mon, 25 Apr 2016 16:09:01 -0700 (PDT) Received: from localhost ([2602:306:c558:19b0:396f:541d:66bc:56f0]) by smtp.gmail.com with ESMTPSA id xm14sm7203394oeb.17.2016.04.25.16.09.00 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Mon, 25 Apr 2016 16:09:01 -0700 (PDT) From: Andy Gross To: linux-arm-msm@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, jilai wang , Stephen Boyd , Andy Gross Subject: [Patch v2 6/8] firmware: qcom: scm: Use atomic SCM for cold boot Date: Mon, 25 Apr 2016 18:08:43 -0500 Message-Id: <1461625725-32425-7-git-send-email-andy.gross@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1461625725-32425-1-git-send-email-andy.gross@linaro.org> References: <1461625725-32425-1-git-send-email-andy.gross@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch changes the cold_set_boot_addr function to use atomic SCM calls. This removes the need for memory allocation and instead places all arguments in registers. Signed-off-by: Andy Gross --- drivers/firmware/qcom_scm-32.c | 47 ++++++++++++++++++++---------------------- 1 file changed, 22 insertions(+), 25 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c index 0d2a3f8..419df4d 100644 --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-32.c @@ -294,34 +294,39 @@ out: (n & 0xf)) /** - * qcom_scm_call_atomic1() - Send an atomic SCM command with one argument + * qcom_scm_call_atomic() - Send an atomic SCM command with one argument * @svc_id: service identifier * @cmd_id: command identifier + * @arglen: number of arguments * @arg1: first argument + * @arg2: second argument (optional - fill with 0 if unused) * * This shall only be used with commands that are guaranteed to be * uninterruptable, atomic and SMP safe. */ -static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1) +static s32 qcom_scm_call_atomic(u32 svc, u32 cmd, u32 arglen, u32 arg1, + u32 arg2) { int context_id; - register u32 r0 asm("r0") = SCM_ATOMIC(svc, cmd, 1); + register u32 r0 asm("r0") = SCM_ATOMIC(svc, cmd, arglen); register u32 r1 asm("r1") = (u32)&context_id; register u32 r2 asm("r2") = arg1; + register u32 r3 asm("r3") = arg2; asm volatile( __asmeq("%0", "r0") __asmeq("%1", "r0") __asmeq("%2", "r1") __asmeq("%3", "r2") + __asmeq("%4", "r3") #ifdef REQUIRES_SEC ".arch_extension sec\n" #endif "smc #0 @ switch to secure world\n" : "=r" (r0) - : "r" (r0), "r" (r1), "r" (r2) - : "r3"); + : "r" (r0), "r" (r1), "r" (r2), "r" (r3) + ); return r0; } @@ -361,22 +366,6 @@ u32 qcom_scm_get_version(void) } EXPORT_SYMBOL(qcom_scm_get_version); -/* - * Set the cold/warm boot address for one of the CPU cores. - */ -static int qcom_scm_set_boot_addr(u32 addr, int flags) -{ - struct { - __le32 flags; - __le32 addr; - } cmd; - - cmd.addr = cpu_to_le32(addr); - cmd.flags = cpu_to_le32(flags); - return qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR, - &cmd, sizeof(cmd), NULL, 0); -} - /** * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus * @entry: Entry point function for the cpus @@ -406,7 +395,8 @@ int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) set_cpu_present(cpu, false); } - return qcom_scm_set_boot_addr(virt_to_phys(entry), flags); + return qcom_scm_call_atomic(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR, 2, + flags, virt_to_phys(entry)); } /** @@ -422,6 +412,10 @@ int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus) int ret; int flags = 0; int cpu; + struct { + __le32 flags; + __le32 addr; + } cmd; /* * Reassign only if we are switching from hotplug entry point @@ -437,7 +431,10 @@ int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus) if (!flags) return 0; - ret = qcom_scm_set_boot_addr(virt_to_phys(entry), flags); + cmd.addr = cpu_to_le32(virt_to_phys(entry)); + cmd.flags = cpu_to_le32(flags); + ret = qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR, + &cmd, sizeof(cmd), NULL, 0); if (!ret) { for_each_cpu(cpu, cpus) qcom_scm_wb[cpu].entry = entry; @@ -456,8 +453,8 @@ int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus) */ void __qcom_scm_cpu_power_down(u32 flags) { - qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC, - flags & QCOM_SCM_FLUSH_FLAG_MASK); + qcom_scm_call_atomic(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC, 1, + flags & QCOM_SCM_FLUSH_FLAG_MASK, 0); } int __qcom_scm_is_call_available(u32 svc_id, u32 cmd_id)