From patchwork Fri Apr 22 22:17:09 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Gross X-Patchwork-Id: 66502 Delivered-To: patch@linaro.org Received: by 10.140.93.198 with SMTP id d64csp962395qge; Fri, 22 Apr 2016 15:18:09 -0700 (PDT) X-Received: by 10.67.1.65 with SMTP id be1mr31736296pad.46.1461363481916; Fri, 22 Apr 2016 15:18:01 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id yx4si9863778pac.109.2016.04.22.15.18.01; Fri, 22 Apr 2016 15:18:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753248AbcDVWRf (ORCPT + 7 others); Fri, 22 Apr 2016 18:17:35 -0400 Received: from mail-ob0-f170.google.com ([209.85.214.170]:33614 "EHLO mail-ob0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753406AbcDVWRb (ORCPT ); Fri, 22 Apr 2016 18:17:31 -0400 Received: by mail-ob0-f170.google.com with SMTP id tz8so55901774obc.0 for ; Fri, 22 Apr 2016 15:17:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gDnAxCIltAbpGk2zSMDZ9F4bqB7W8EBAup6JsVNSy+g=; b=WTBNfWppjyRza1erKtBfHvjFzZy1zy3c2F7cWZLBMqjw4nqs58rSolpgPCpvHkh+B1 KDYIaxmM7LS5B7aDYGqk6jHeHiHnKNIJHsQIMRbx41Bd48ms/qW7TMpiAjQwzBCxYx0T sJtj6Fmv+jZAkoMLFDiLUklvNk3EfYHDjpWNc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gDnAxCIltAbpGk2zSMDZ9F4bqB7W8EBAup6JsVNSy+g=; b=mq0vKkybq5d0nfKncezsnXzaGTwy1OwdN8Y+ZFIq0fpxrfzXn8ycFzLBfFOvWcQDMo MgM0yRPYgAEQ0/gg8z0R4Mn4NeilIXstUo+cgOGrxOtDr33EM/TB+zNJPfVIFd3H7VCp p8xbmXOv/PMXXEvjHEoB9Br5lnOXGeWgWtT8PS0tSS3X/ECiBM+fy3jbSo/UZPoeczZY PWet0aVD6eMVPjg9KsobZ6PiIBe24Zq3zORDZSV8l/sqbCbzcUCflnLnKgiH1dqXwvBf VI6aHK5gkj5Amruyn92rZco7IV9rpPQb7WUNTHnOWg6GK3LL0TPHpz4Jjpb8Dd2utlGb FioQ== X-Gm-Message-State: AOPr4FUe5YCNIm8bjIuOSy12vHRMYXPQaf4iUn1Whz4O3KnbLfQi65X2uoENLX3cPyrGbCYt X-Received: by 10.60.67.101 with SMTP id m5mr10290251oet.19.1461363449910; Fri, 22 Apr 2016 15:17:29 -0700 (PDT) Received: from localhost ([2602:306:c558:19b0:a419:15a3:ad7f:f979]) by smtp.gmail.com with ESMTPSA id t3sm2648966oem.3.2016.04.22.15.17.29 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Fri, 22 Apr 2016 15:17:29 -0700 (PDT) From: Andy Gross To: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Stephen Boyd , devicetree@vger.kernel.org, Bjorn Andersson , jilai wang , Andy Gross Subject: [PATCH 5/8] firmware: qcom: scm: Use atomic SCM for cold boot Date: Fri, 22 Apr 2016 17:17:09 -0500 Message-Id: <1461363432-5730-6-git-send-email-andy.gross@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1461363432-5730-1-git-send-email-andy.gross@linaro.org> References: <1461363432-5730-1-git-send-email-andy.gross@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch changes the cold_set_boot_addr function to use atomic SCM calls. This removes the need for memory allocation and instead places all arguments in registers. Signed-off-by: Andy Gross --- drivers/firmware/qcom_scm-32.c | 40 ++++++++++++++++++++++++++-------------- 1 file changed, 26 insertions(+), 14 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c index 0d2a3f8..f596091 100644 --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-32.c @@ -294,34 +294,39 @@ out: (n & 0xf)) /** - * qcom_scm_call_atomic1() - Send an atomic SCM command with one argument + * qcom_scm_call_atomic() - Send an atomic SCM command with one argument * @svc_id: service identifier * @cmd_id: command identifier + * @arglen: number of arguments * @arg1: first argument + * @arg2: second argument (optional - fill with 0 if unused) * * This shall only be used with commands that are guaranteed to be * uninterruptable, atomic and SMP safe. */ -static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1) +static s32 qcom_scm_call_atomic(u32 svc, u32 cmd, u32 arglen, u32 arg1, + u32 arg2) { int context_id; - register u32 r0 asm("r0") = SCM_ATOMIC(svc, cmd, 1); + register u32 r0 asm("r0") = SCM_ATOMIC(svc, cmd, arglen); register u32 r1 asm("r1") = (u32)&context_id; register u32 r2 asm("r2") = arg1; + register u32 r3 asm("r3") = arg2; asm volatile( __asmeq("%0", "r0") __asmeq("%1", "r0") __asmeq("%2", "r1") __asmeq("%3", "r2") + __asmeq("%4", "r3") #ifdef REQUIRES_SEC ".arch_extension sec\n" #endif "smc #0 @ switch to secure world\n" : "=r" (r0) - : "r" (r0), "r" (r1), "r" (r2) - : "r3"); + : "r" (r0), "r" (r1), "r" (r2), "r" (r3) + ); return r0; } @@ -364,17 +369,24 @@ EXPORT_SYMBOL(qcom_scm_get_version); /* * Set the cold/warm boot address for one of the CPU cores. */ -static int qcom_scm_set_boot_addr(u32 addr, int flags) +static int qcom_scm_set_boot_addr(u32 addr, int flags, bool do_atomic) { struct { __le32 flags; __le32 addr; } cmd; - cmd.addr = cpu_to_le32(addr); - cmd.flags = cpu_to_le32(flags); - return qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR, - &cmd, sizeof(cmd), NULL, 0); + if (do_atomic) { + return qcom_scm_call_atomic(QCOM_SCM_SVC_BOOT, + QCOM_SCM_BOOT_ADDR, 2, flags, addr); + } else { + + cmd.addr = cpu_to_le32(addr); + cmd.flags = cpu_to_le32(flags); + + return qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR, + &cmd, sizeof(cmd), NULL, 0); + } } /** @@ -406,7 +418,7 @@ int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) set_cpu_present(cpu, false); } - return qcom_scm_set_boot_addr(virt_to_phys(entry), flags); + return qcom_scm_set_boot_addr(virt_to_phys(entry), flags, true); } /** @@ -437,7 +449,7 @@ int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus) if (!flags) return 0; - ret = qcom_scm_set_boot_addr(virt_to_phys(entry), flags); + ret = qcom_scm_set_boot_addr(virt_to_phys(entry), flags, false); if (!ret) { for_each_cpu(cpu, cpus) qcom_scm_wb[cpu].entry = entry; @@ -456,8 +468,8 @@ int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus) */ void __qcom_scm_cpu_power_down(u32 flags) { - qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC, - flags & QCOM_SCM_FLUSH_FLAG_MASK); + qcom_scm_call_atomic(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC, 1, + flags & QCOM_SCM_FLUSH_FLAG_MASK, 0); } int __qcom_scm_is_call_available(u32 svc_id, u32 cmd_id)