From patchwork Thu Apr 14 11:08:09 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 65800 Delivered-To: patch@linaro.org Received: by 10.140.93.198 with SMTP id d64csp529914qge; Thu, 14 Apr 2016 04:09:45 -0700 (PDT) X-Received: by 10.66.180.68 with SMTP id dm4mr3242093pac.76.1460632169878; Thu, 14 Apr 2016 04:09:29 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b5si7243168pat.133.2016.04.14.04.09.29; Thu, 14 Apr 2016 04:09:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754980AbcDNLJ2 (ORCPT + 7 others); Thu, 14 Apr 2016 07:09:28 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:54400 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754885AbcDNLJZ (ORCPT ); Thu, 14 Apr 2016 07:09:25 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id u3EB8uRj014851; Thu, 14 Apr 2016 06:08:56 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id u3EB8u5F011093; Thu, 14 Apr 2016 06:08:56 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.224.2; Thu, 14 Apr 2016 06:08:55 -0500 Received: from sokoban.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id u3EB86JU005701; Thu, 14 Apr 2016 06:08:53 -0500 From: Tero Kristo To: , , , , CC: , , Subject: [PATCHv2 20/28] clk: ti: mux: export mux clock APIs locally Date: Thu, 14 Apr 2016 14:08:09 +0300 Message-ID: <1460632097-25727-21-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1460632097-25727-1-git-send-email-t-kristo@ti.com> References: <1460632097-25727-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org get_parent and set_parent are going to be required by the support of module clocks, so export these locally. Signed-off-by: Tero Kristo --- drivers/clk/ti/clock.h | 3 +++ drivers/clk/ti/mux.c | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h index 90f3f47..7eca8a1 100644 --- a/drivers/clk/ti/clock.h +++ b/drivers/clk/ti/clock.h @@ -224,6 +224,9 @@ extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait; extern const struct clk_ops ti_clk_divider_ops; extern const struct clk_ops ti_clk_mux_ops; +u8 ti_clk_mux_get_parent(struct clk_hw *hw); +int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index); + int omap2_clkops_enable_clkdm(struct clk_hw *hw); void omap2_clkops_disable_clkdm(struct clk_hw *hw); diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c index 44777ab..57ff471 100644 --- a/drivers/clk/ti/mux.c +++ b/drivers/clk/ti/mux.c @@ -26,7 +26,7 @@ #undef pr_fmt #define pr_fmt(fmt) "%s: " fmt, __func__ -static u8 ti_clk_mux_get_parent(struct clk_hw *hw) +u8 ti_clk_mux_get_parent(struct clk_hw *hw) { struct clk_mux *mux = to_clk_mux(hw); int num_parents = clk_hw_get_num_parents(hw); @@ -63,7 +63,7 @@ static u8 ti_clk_mux_get_parent(struct clk_hw *hw) return val; } -static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index) +int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index) { struct clk_mux *mux = to_clk_mux(hw); u32 val;