From patchwork Fri Mar 25 15:36:26 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 64496 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp230843lbc; Fri, 25 Mar 2016 08:37:35 -0700 (PDT) X-Received: by 10.66.193.161 with SMTP id hp1mr22033122pac.9.1458920255492; Fri, 25 Mar 2016 08:37:35 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q82si4011448pfi.220.2016.03.25.08.37.35; Fri, 25 Mar 2016 08:37:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753865AbcCYPhd (ORCPT + 7 others); Fri, 25 Mar 2016 11:37:33 -0400 Received: from mail-wm0-f46.google.com ([74.125.82.46]:37222 "EHLO mail-wm0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753379AbcCYPgg (ORCPT ); Fri, 25 Mar 2016 11:36:36 -0400 Received: by mail-wm0-f46.google.com with SMTP id p65so26763622wmp.0 for ; Fri, 25 Mar 2016 08:36:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PmQl58rXsTrlLF+ND6KDLbw2UCIHsVgUSumGjM5aksk=; b=RRombEGRj5ODegCHwFvznsM9rVpu5cZue1Up95T7X0BxjxRlTnklda+KCVngw7DEz+ pQfmAcsOW7sDeGfWvOhyJTKsjjSB6U+ftyvs0B/Wo4fZYSeHVn/pHKwyvl9h7ivsPiwQ PxW7VYNjAgd3CgEpqs3mKOVv8yLe+Q7r1dIJM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PmQl58rXsTrlLF+ND6KDLbw2UCIHsVgUSumGjM5aksk=; b=KfKMT65KeXS76M2nJBEV9SaGCC89req9Ki0OwJn7ZQ5yPA8XTK6A01bIG8LVFn9O31 i+IMZyCOwAdWyeoV8jc3MBBh3LEB7R1SiUzhpyjieAWv7afQjLIwLurbV1vtet5qCD7u ecN3MqF6Gq8DFVUNFU8AEQtZTtNybRzQ63Cl/fNNPL9xSpjulIGBjzdtv+BqNpHhu9Bv MH9TizPEl3uCIv3Y/b7xl0qJ5O5tgbX4KLcNRfOjUaXPy9UqJIuwkvq6wp8+agrN5RD3 4QUJRBna6mSDgsJn6Q0sSZcBD30Zg1pZwH0gGtO/UmM28nuJZsvgbZ9KAOfaVa2tzP+G /1pg== X-Gm-Message-State: AD7BkJIR9FF5NBfDwgJHMkFitrKp/v8wLIelX4tWHdtImTah6cFbHDMhZG5eqbxtaElwC4+X X-Received: by 10.194.223.104 with SMTP id qt8mr15986920wjc.11.1458920195427; Fri, 25 Mar 2016 08:36:35 -0700 (PDT) Received: from localhost.localdomain (cpc84787-aztw28-2-0-cust15.18-1.cable.virginm.net. [82.37.140.16]) by smtp.gmail.com with ESMTPSA id q139sm3627832wmd.2.2016.03.25.08.36.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 25 Mar 2016 08:36:34 -0700 (PDT) From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, maxime.coquelin@st.com, patrice.chotard@st.com, srinivas.kandagatla@gmail.com Cc: peter.griffin@linaro.org, lee.jones@linaro.org, devicetree@vger.kernel.org Subject: [PATCH 2/4] ARM: DT: STiH407: Add i2c12 pin definition Date: Fri, 25 Mar 2016 15:36:26 +0000 Message-Id: <1458920188-29612-3-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1458920188-29612-1-git-send-email-peter.griffin@linaro.org> References: <1458920188-29612-1-git-send-email-peter.griffin@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT pinctrl definitions for SSC12 controller. Signed-off-by: Peter Griffin --- arch/arm/boot/dts/stih407-pinctrl.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi index 87e75bf..e647751 100644 --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi @@ -203,6 +203,15 @@ }; }; + i2c12 { + pinctrl_i2c12_default: i2c12-default { + st,pins { + sda = <&pio3 6 ALT2 BIDIR>; + scl = <&pio3 7 ALT2 BIDIR>; + }; + }; + }; + keyscan { pinctrl_keyscan: keyscan { st,pins {