From patchwork Fri Nov 20 02:25:07 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Feng X-Patchwork-Id: 57060 Delivered-To: patch@linaro.org Received: by 10.112.155.196 with SMTP id vy4csp208030lbb; Thu, 19 Nov 2015 18:28:45 -0800 (PST) X-Received: by 10.66.165.39 with SMTP id yv7mr15816647pab.108.1447986525456; Thu, 19 Nov 2015 18:28:45 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id pc5si16107041pbb.169.2015.11.19.18.28.45; Thu, 19 Nov 2015 18:28:45 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934901AbbKTC2n (ORCPT + 6 others); Thu, 19 Nov 2015 21:28:43 -0500 Received: from szxga03-in.huawei.com ([119.145.14.66]:25713 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934033AbbKTC2n (ORCPT ); Thu, 19 Nov 2015 21:28:43 -0500 Received: from 172.24.1.51 (EHLO SZXEML429-HUB.china.huawei.com) ([172.24.1.51]) by szxrg03-dlp.huawei.com (MOS 4.4.3-GA FastPath queued) with ESMTP id BRI11985; Fri, 20 Nov 2015 10:25:21 +0800 (CST) Received: from vm163-62.huawei.com (10.184.163.62) by SZXEML429-HUB.china.huawei.com (10.82.67.184) with Microsoft SMTP Server id 14.3.235.1; Fri, 20 Nov 2015 10:25:11 +0800 From: Chen Feng To: , , , , , , , , CC: , , , , , Subject: [PATCH V5 RESEND 1/3] docs: iommu: Documentation for iommu in hi6220 SoC Date: Fri, 20 Nov 2015 10:25:07 +0800 Message-ID: <1447986309-47548-2-git-send-email-puck.chen@hisilicon.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1447986309-47548-1-git-send-email-puck.chen@hisilicon.com> References: <1447986309-47548-1-git-send-email-puck.chen@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.184.163.62] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A0B0206.564E8493.0053, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: d094dffff6c8c019ba956752c06347f3 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Documentation for hi6220 iommu driver. Signed-off-by: Chen Feng --- .../bindings/iommu/hisi,hi6220-iommu.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt b/Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt new file mode 100644 index 0000000..44f9101 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt @@ -0,0 +1,32 @@ +Hi6220 SoC SMMU Device Driver devicetree document +The media system shared the same smmu IP to access DDR memory. And all +media IP used the same page table. + +Below binding describes the system mmu for media system in hi6220 platform + +Required properties: +- compatible: should contain "hisilicon,hi6220-smmu". +- reg: A tuple of base address and size of System MMU registers. +- clocks: a list of phandle + clock-specifier pairs, one for each entry + in clock-names. +- clock-names: should contain: + * "smmu" + * "media-sc" + * "smmu-peri" +- interrupts: An interrupt specifier for interrupt signal of System MMU. +- #iommu-cells: The iommu-cells should be 0. Because no additional information + needs to be encoded in the specifier. + +Examples: + iommu@f4210000 { + compatible = "hisilicon,hi6220-smmu"; + reg = <0x0 0xf4210000 0x0 0x1000>; + interrupts = ; + clocks = <&sys_ctrl HI6220_MMU_CLK>, + <&media_ctrl HI6220_MED_MMU>, + <&sys_ctrl HI6220_MEDIA_PLL_SRC>; + clock-names = "smmu", + "media-sc", + "smmu-peri"; + #iommu-cells = <0>; + };