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[209.132.180.67]) by mx.google.com with ESMTP id bz7si7771540pab.40.2015.10.13.14.22.50; Tue, 13 Oct 2015 14:22:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932393AbbJMVWt (ORCPT + 7 others); Tue, 13 Oct 2015 17:22:49 -0400 Received: from mail-gw1-out.broadcom.com ([216.31.210.62]:53483 "EHLO mail-gw1-out.broadcom.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932325AbbJMVWs (ORCPT ); Tue, 13 Oct 2015 17:22:48 -0400 X-IronPort-AV: E=Sophos;i="5.17,680,1437462000"; d="scan'208";a="77615960" Received: from irvexchcas08.broadcom.com (HELO IRVEXCHCAS08.corp.ad.broadcom.com) ([10.9.208.57]) by mail-gw1-out.broadcom.com with ESMTP; 13 Oct 2015 16:15:34 -0700 Received: from IRVEXCHSMTP1.corp.ad.broadcom.com (10.9.207.51) by IRVEXCHCAS08.corp.ad.broadcom.com (10.9.208.57) with Microsoft SMTP Server (TLS) id 14.3.235.1; Tue, 13 Oct 2015 14:22:47 -0700 Received: from mail-irva-13.broadcom.com (10.10.10.20) by IRVEXCHSMTP1.corp.ad.broadcom.com (10.9.207.51) with Microsoft SMTP Server id 14.3.235.1; Tue, 13 Oct 2015 14:22:47 -0700 Received: from venom.rtp.broadcom.com (unknown [10.27.64.103]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 4CA2E4104E; Tue, 13 Oct 2015 14:19:46 -0700 (PDT) From: Jon Mason To: Michael Turquette , Stephen Boyd CC: Florian Fainelli , Hauke Mehrtens , Ray Jui , Scott Branden , , , , , Subject: [RFC 5/5] ARM: dts: enable clock support for Broadcom NS2 Date: Tue, 13 Oct 2015 17:22:27 -0400 Message-ID: <1444771347-11382-6-git-send-email-jonmason@broadcom.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1444771347-11382-1-git-send-email-jonmason@broadcom.com> References: <1444771347-11382-1-git-send-email-jonmason@broadcom.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: jonmason@broadcom.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.174 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add device tree entries for clock support for Broadcom Northstar 2 SoC Signed-off-by: Jon Mason --- arch/arm64/boot/dts/broadcom/ns2.dtsi | 93 ++++++++++++++++++++++++++++++++--- 1 file changed, 86 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index 3c92d92..c632f3b 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -31,6 +31,7 @@ */ #include +#include /memreserve/ 0x84b00000 0x00000008; @@ -89,25 +90,103 @@ IRQ_TYPE_EDGE_RISING)>; }; + clocks { + #address-cells = <1>; + #size-cells = <1>; + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + iprocmed: iprocmed { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; + clock-div = <2>; + clock-mult = <1>; + }; + + iprocslow: iprocslow { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + soc: soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + ranges = <0 0 0x65000000 0x01130100>; + + lcpll_ddr: lcpll_ddr@001d058 { + #clock-cells = <1>; + compatible = "brcm,ns2-lcpll-ddr"; + reg = <0x001d058 0x20>, + <0x001c020 0x4>, + <0x001d04c 0x4>; + clocks = <&osc>; + clock-output-names = "lcpll_ddr", "pcie_sata_usb", + "ddr", "ddr_ch2_unused", + "ddr_ch3_unused", "ddr_ch4_unused", + "ddr_ch5_unused"; + }; + + lcpll_ports: lcpll_ports@1d078 { + #clock-cells = <1>; + compatible = "brcm,ns2-lcpll-ports"; + reg = <0x001d078 0x20>, + <0x001c020 0x4>, + <0x001d054 0x4>; + clocks = <&osc>; + clock-output-names = "lcpll_ports", "wan", "rgmii", + "ports_ch2_unused", + "ports_ch3_unused", + "ports_ch4_unused", + "ports_ch5_unused"; + }; + + genpll_scr: genpll_scr@001d098 { + #clock-cells = <1>; + compatible = "brcm,ns2-genpll-scr"; + reg = <0x001d098 0x32>, + <0x001c020 0x4>, + <0x001d044 0x4>; + clocks = <&osc>; + clock-output-names = "genpll_scr", "scr", "fs", + "audio_ref", "scr_ch3_unused", + "scr_ch4_unused", "scr_ch5_unused"; + }; + + genpll_sw: genpll_sw@001d0c4 { + #clock-cells = <1>; + compatible = "brcm,ns2-genpll-sw"; + reg = <0x001d0c4 0x32>, + <0x001c020 0x4>, + <0x001d044 0x4>; + clocks = <&osc>; + clock-output-names = "genpll_sw", "rpe", "250", "nic", + "chimp", "port", "sdio"; + }; - gic: interrupt-controller@65210000 { + gic: interrupt-controller@0210000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; interrupt-controller; - reg = <0x65210000 0x1000>, - <0x65220000 0x1000>, - <0x65240000 0x2000>, - <0x65260000 0x1000>; + reg = <0x0210000 0x1000>, + <0x0220000 0x1000>, + <0x0240000 0x2000>, + <0x0260000 0x1000>; }; - uart3: serial@66130000 { + uart3: serial@1130000 { compatible = "snps,dw-apb-uart"; - reg = <0x66130000 0x100>; + reg = <0x1130000 0x100>; interrupts = ; reg-shift = <2>; reg-io-width = <4>;