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[209.132.180.67]) by mx.google.com with ESMTP id gu6si9028377obb.49.2015.10.12.08.08.19; Mon, 12 Oct 2015 08:08:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751464AbbJLPIS (ORCPT + 7 others); Mon, 12 Oct 2015 11:08:18 -0400 Received: from szxga02-in.huawei.com ([119.145.14.65]:12538 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751457AbbJLPIR (ORCPT ); Mon, 12 Oct 2015 11:08:17 -0400 Received: from 172.24.1.51 (EHLO szxeml432-hub.china.huawei.com) ([172.24.1.51]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CUB61516; Mon, 12 Oct 2015 23:05:10 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by szxeml432-hub.china.huawei.com (10.82.67.209) with Microsoft SMTP Server id 14.3.235.1; Mon, 12 Oct 2015 23:05:00 +0800 From: John Garry To: CC: , , , , , , , , , John Garry Subject: [PATCH 02/25] devicetree: bindings: scsi: HiSi SAS Date: Mon, 12 Oct 2015 23:20:14 +0800 Message-ID: <1444663237-238302-3-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1444663237-238302-1-git-send-email-john.garry@huawei.com> References: <1444663237-238302-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: john.garry@huawei.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.175 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add devicetree bindings for HiSilicon SAS driver. Signed-off-by: John Garry --- .../devicetree/bindings/scsi/hisilicon-sas.txt | 63 ++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/scsi/hisilicon-sas.txt diff --git a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt new file mode 100644 index 0000000..472c022 --- /dev/null +++ b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt @@ -0,0 +1,63 @@ +* HiSilison SAS controller + +The HiSilicon SAS controller supports SAS/SATA. + +Main node required properties: + - compatible : value should be as follows: + (a) "hisilicon,sas-controller-v1" for v1 of HiSilicon SAS controller IP + + - controller-id : identifier for controller in the SoC + + - reg : Address and length of the register sets for the device + - SAS controller registers + - SAS controller control registers + + - reset-reg : offset to reset, status, and clock registers in control registers + + - queue-count : number of delivery and completion queues in the controller + + - phy-count : number of phys accessible by the controller + + - interrupts : Interrupts for phys, completion queues, and fatal + interrupts: + - Each phy has 3 interrupt sources: + - broadcast + - phyup + - abnormal + - Each completion queue has 1 interrupt source + - Each controller has 2 fatal interrupt sources: + - ECC + - AXI bus + +Example: + sas0: sas@c1000000 { + compatible = "hisilicon,sas-controller-v1"; + controller-id = <0>; + reg = <0x0 0xc1000000 0x0 0x10000>, + <0x0 0xc0000000 0x0 0x10000>; + reset-reg = <0xa60 0x33c 0x5a30 0xa64 0x338>; + queue-count = <32>; + phy-count = <8>; + #interrupt-cells = <2>; + dma-coherent; + interrupt-parent = <&mbigen_dsa>; + interrupts = <259 4>, <263 4>,<264 4>,/* phy irq(0~79) */ + <269 4>,<273 4>,<274 4>,/* phy irq(0~79) */ + <279 4>,<283 4>,<284 4>,/* phy irq(0~79) */ + <289 4>,<293 4>,<294 4>,/* phy irq(0~79) */ + <299 4>,<303 4>,<304 4>,/* phy irq(0~79) */ + <309 4>,<313 4>,<314 4>,/* phy irq(0~79) */ + <319 4>,<323 4>,<324 4>,/* phy irq(0~79) */ + <329 4>,<333 4>,<334 4>,/* phy irq(0~79) */ + <336 1>,<337 1>,<338 1>,<339 1>,<340 1>, + <341 1>,<342 1>,<343 1>,/* cq irq (80~111) */ + <344 1>,<345 1>,<346 1>,<347 1>,<348 1>, + <349 1>,<350 1>,<351 1>,/* cq irq (80~111) */ + <352 1>,<353 1>,<354 1>,<355 1>,<356 1>, + <357 1>,<358 1>,<359 1>,/* cq irq (80~111) */ + <360 1>,<361 1>,<362 1>,<363 1>,<364 1>, + <365 1>,<366 1>,<367 1>,/* cq irq (80~111) */ + <376 4>,/* chip fatal error irq(120) */ + <381 4>;/* chip fatal error irq(125) */ + status = "okay"; + };