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[209.85.217.173]) by mx.google.com with ESMTPS id k186si29770889lfb.81.2015.10.08.06.31.48 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Oct 2015 06:31:48 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.173 as permitted sender) client-ip=209.85.217.173; Received: by lbos8 with SMTP id s8so46572273lbo.0 for ; Thu, 08 Oct 2015 06:31:48 -0700 (PDT) X-Received: by 10.112.180.230 with SMTP id dr6mr3678166lbc.72.1444311107885; Thu, 08 Oct 2015 06:31:47 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.59.35 with SMTP id w3csp589748lbq; Thu, 8 Oct 2015 06:31:46 -0700 (PDT) X-Received: by 10.66.157.135 with SMTP id wm7mr8252733pab.22.1444311106414; Thu, 08 Oct 2015 06:31:46 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id pr9si66591881pbc.59.2015.10.08.06.31.46; Thu, 08 Oct 2015 06:31:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932819AbbJHNbh (ORCPT + 30 others); Thu, 8 Oct 2015 09:31:37 -0400 Received: from bhuna.collabora.co.uk ([93.93.135.160]:60473 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932617AbbJHNbb (ORCPT ); Thu, 8 Oct 2015 09:31:31 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: sjoerd) with ESMTPSA id 01D596092C1 Received: by dusk.luon.net (Postfix, from userid 1000) id BBBD924ED8; Thu, 8 Oct 2015 15:31:19 +0200 (CEST) From: Sjoerd Simons To: linux-rockchip@lists.infradead.org Cc: Jaroslav Kysela , devicetree@vger.kernel.org, alsa-devel@alsa-project.org, Heiko Stuebner , Mark Brown , linux-kernel@vger.kernel.org, Kumar Gala , Ian Campbell , Takashi Iwai , Liam Girdwood , Sjoerd Simons , Pawel Moll , Rob Herring , Mark Rutland , Russell King , linux-arm-kernel@lists.infradead.org, Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org Subject: [PATCH v4 5/8] clk: rockchip: Allow the RK3288 SPDIF clocks to change their parent Date: Thu, 8 Oct 2015 15:31:16 +0200 Message-Id: <1444311079-2892-6-git-send-email-sjoerd.simons@collabora.co.uk> X-Mailer: git-send-email 2.6.1 In-Reply-To: <1444311079-2892-1-git-send-email-sjoerd.simons@collabora.co.uk> References: <1444311079-2892-1-git-send-email-sjoerd.simons@collabora.co.uk> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: sjoerd.simons@collabora.co.uk X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.173 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The clock branches leading to sclk_spdif and sclk_spdif_8ch on RK3288 SoCs only feed those clocks, allow those clocks to change their parents all the way up the hierarchy. Signed-off-by: Sjoerd Simons Reviewed-by: Heiko Stuebner --- Changes in v4: None Changes in v3: None Changes in v2: None drivers/clk/rockchip/clk-rk3288.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index 90c1c9b..4e90252 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -317,25 +317,25 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0, RK3288_CLKSEL_CON(5), 15, 1, MFLAGS), - COMPOSITE_NOMUX(0, "spdif_pre", "spdif_src", 0, + COMPOSITE_NOMUX(0, "spdif_pre", "spdif_src", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(5), 0, 7, DFLAGS, RK3288_CLKGATE_CON(4), 4, GFLAGS), - COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", 0, + COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(9), 0, RK3288_CLKGATE_CON(4), 5, GFLAGS, - MUX(0, "spdif_mux", mux_spdif_p, 0, + MUX(0, "spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(5), 8, 2, MFLAGS)), - GATE(SCLK_SPDIF, "sclk_spdif", "spdif_mux", 0, + GATE(SCLK_SPDIF, "sclk_spdif", "spdif_mux", CLK_SET_RATE_PARENT, RK3288_CLKGATE_CON(4), 6, GFLAGS), - COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", 0, + COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(40), 0, 7, DFLAGS, RK3288_CLKGATE_CON(4), 7, GFLAGS), - COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_pre", 0, + COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_pre", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(41), 0, RK3288_CLKGATE_CON(4), 8, GFLAGS, - MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, 0, + MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(40), 8, 2, MFLAGS)), - GATE(SCLK_SPDIF8CH, "sclk_spdif_8ch", "spdif_8ch_mux", 0, + GATE(SCLK_SPDIF8CH, "sclk_spdif_8ch", "spdif_8ch_mux", CLK_SET_RATE_PARENT, RK3288_CLKGATE_CON(4), 9, GFLAGS), GATE(0, "sclk_acc_efuse", "xin24m", 0,