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[209.132.180.67]) by mx.google.com with ESMTP id r2si19239923pap.80.2015.09.07.02.49.22; Mon, 07 Sep 2015 02:49:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752590AbbIGJtV (ORCPT + 8 others); Mon, 7 Sep 2015 05:49:21 -0400 Received: from foss.arm.com ([217.140.101.70]:50150 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751772AbbIGJtV (ORCPT ); Mon, 7 Sep 2015 05:49:21 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E742375; Mon, 7 Sep 2015 02:49:28 -0700 (PDT) Received: from leverpostej.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C079A3F318; Mon, 7 Sep 2015 02:49:19 -0700 (PDT) From: Mark Rutland To: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, marc.zyngier@arm.com, Mark Rutland , Rob Herring Subject: [PATCH] Docs: dt: add #msi-cells to GICv3 ITS binding Date: Mon, 7 Sep 2015 10:49:03 +0100 Message-Id: <1441619343-12087-1-git-send-email-mark.rutland@arm.com> X-Mailer: git-send-email 1.9.1 Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: mark.rutland@arm.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.44 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The GICv3 ITS uses sideband master identification data (known as a DeviceID) to identify which master wrote to a doorbell, and this data is used to determine how to react in response to the write. Commit 1e6db000482fa65a ("irqchip/gicv3-its: Add platform MSI support") added support per this binding, but failed to update the documentation. This patch fixes the documentation. Signed-off-by: Mark Rutland Acked-by: Marc Zyngier Cc: Rob Herring --- Documentation/devicetree/bindings/arm/gic-v3.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/gic-v3.txt b/Documentation/devicetree/bindings/arm/gic-v3.txt index ddfade4..7803e77 100644 --- a/Documentation/devicetree/bindings/arm/gic-v3.txt +++ b/Documentation/devicetree/bindings/arm/gic-v3.txt @@ -57,6 +57,8 @@ used to route Message Signalled Interrupts (MSI) to the CPUs. These nodes must have the following properties: - compatible : Should at least contain "arm,gic-v3-its". - msi-controller : Boolean property. Identifies the node as an MSI controller +- #msi-cells: Must be <1>. The single msi-cell is the DeviceID of the device + which will generate the MSI. - reg: Specifies the base physical address and size of the ITS registers. @@ -83,6 +85,7 @@ Examples: gic-its@2c200000 { compatible = "arm,gic-v3-its"; msi-controller; + #msi-cells = <1>; reg = <0x0 0x2c200000 0 0x200000>; }; }; @@ -107,12 +110,14 @@ Examples: gic-its@2c200000 { compatible = "arm,gic-v3-its"; msi-controller; + #msi-cells = <1>; reg = <0x0 0x2c200000 0 0x200000>; }; gic-its@2c400000 { compatible = "arm,gic-v3-its"; msi-controller; + #msi-cells = <1>; reg = <0x0 0x2c400000 0 0x200000>; }; };