From patchwork Wed Jul 1 02:16:44 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "pi-cheng.chen" X-Patchwork-Id: 50503 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wi0-f200.google.com (mail-wi0-f200.google.com [209.85.212.200]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 4A9CC218E4 for ; Wed, 1 Jul 2015 02:19:02 +0000 (UTC) Received: by wiwz6 with SMTP id z6sf12153512wiw.0 for ; Tue, 30 Jun 2015 19:19:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:subject:date:message-id :in-reply-to:references:precedence:list-id:list-unsubscribe :list-archive:list-post:list-help:list-subscribe:cc:mime-version :content-type:content-transfer-encoding:sender:errors-to :x-original-sender:x-original-authentication-results:mailing-list; bh=aXjgDCzcFA4qwoRxFw/yZmtYAIBNmCm0UuAUkTi97o0=; b=BtGFVZ7rztf4c98IDfDC2clGIhq4dKUyMo90UZ2eOlN03YLYMH3jxLpvBRBMDHNPPk Ve6cw/kXazKsm+SLGkgKqsPxRRfl2QcN+m0Tn243WWQBMx3hTewAzTthSOUtkyha3rxo 7nvH8BRL139P04hHpmem9E+cKfmiOFI3Ooes0v8zxF9rWr44/XfKX7yneKEFTft5HlVv bSksg7j/zYiySCgVc+Q84Y54+llm6/Gj2n73F2+XGwxxxc1Z2Omzzvhvn3FVK7KCAg4D TjQ2jXRp1EUHK2J05n5LOwP6oBdVP/pDiI0OSDG99qdKOQPFZCJ+q+P7CtMTTDIKLE+n 5fsA== X-Gm-Message-State: ALoCoQmDcflPQiNUCfP31JIQqqOBwtFh42h3yaZVeiPVBKgPxAuluwbX2McqMJt83car1bhCLvH+ X-Received: by 10.180.105.226 with SMTP id gp2mr13514865wib.1.1435717142026; Tue, 30 Jun 2015 19:19:02 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.23.103 with SMTP id l7ls130537laf.35.gmail; Tue, 30 Jun 2015 19:19:01 -0700 (PDT) X-Received: by 10.152.37.196 with SMTP id a4mr22859189lak.59.1435717141860; Tue, 30 Jun 2015 19:19:01 -0700 (PDT) Received: from mail-la0-f53.google.com (mail-la0-f53.google.com. [209.85.215.53]) by mx.google.com with ESMTPS id jd11si319980lac.80.2015.06.30.19.19.01 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 30 Jun 2015 19:19:01 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.53 as permitted sender) client-ip=209.85.215.53; Received: by lagh6 with SMTP id h6so31507049lag.2 for ; Tue, 30 Jun 2015 19:19:01 -0700 (PDT) X-Received: by 10.112.198.74 with SMTP id ja10mr22633475lbc.19.1435717141439; Tue, 30 Jun 2015 19:19:01 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.108.230 with SMTP id hn6csp284835lbb; Tue, 30 Jun 2015 19:19:00 -0700 (PDT) X-Received: by 10.68.190.41 with SMTP id gn9mr48702090pbc.113.1435717134954; Tue, 30 Jun 2015 19:18:54 -0700 (PDT) Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id w10si616197pdo.223.2015.06.30.19.18.54 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 30 Jun 2015 19:18:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZA7aZ-0003wj-Fz; Wed, 01 Jul 2015 02:17:27 +0000 Received: from mail-pd0-f177.google.com ([209.85.192.177]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZA7aR-0003p2-3Q for linux-arm-kernel@lists.infradead.org; Wed, 01 Jul 2015 02:17:20 +0000 Received: by pdcu2 with SMTP id u2so16583181pdc.3 for ; Tue, 30 Jun 2015 19:16:58 -0700 (PDT) X-Received: by 10.66.90.166 with SMTP id bx6mr49427381pab.76.1435717018785; Tue, 30 Jun 2015 19:16:58 -0700 (PDT) Received: from localhost.localdomain ([124.219.30.17]) by mx.google.com with ESMTPSA id oe10sm268605pdb.19.2015.06.30.19.16.55 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 30 Jun 2015 19:16:58 -0700 (PDT) From: Pi-Cheng Chen To: Viresh Kumar , Michael Turquette , Matthias Brugger , Mark Rutland Subject: [PATCH v5 1/2] dt-bindings: mediatek: Add MT8173 cpufreq driver binding Date: Wed, 1 Jul 2015 10:16:44 +0800 Message-Id: <1435717005-20012-2-git-send-email-pi-cheng.chen@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1435717005-20012-1-git-send-email-pi-cheng.chen@linaro.org> References: <1435717005-20012-1-git-send-email-pi-cheng.chen@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150630_191719_238950_94172E4E X-CRM114-Status: GOOD ( 17.53 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.192.177 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [209.85.192.177 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Cc: devicetree@vger.kernel.org, linaro-kernel@lists.linaro.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: pi-cheng.chen@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.53 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 This patch adds device tree binding document for MT8173 cpufreq driver. Signed-off-by: Pi-Cheng Chen Reviewed-by: Michael Turquette --- .../devicetree/bindings/cpufreq/cpufreq-mt8173.txt | 145 +++++++++++++++++++++ 1 file changed, 145 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt new file mode 100644 index 0000000..65701c5 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt @@ -0,0 +1,145 @@ + +Mediatek MT8173 cpufreq driver +------------------------------ + +Mediatek MT8173 cpufreq driver for CPU frequency scaling. + +Required properties: +- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names. +- clock-names: Should contain the following: + "cpu" - The multiplexer for clock input of CPU cluster. + "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock + source (usually MAINPLL) when the original CPU PLL is under + transition and not stable yet. + Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for + generic clock consumer properties. +- operating-points: Please refer to Documentation/devicetree/bindings/power/opp.txt for + details. +- proc-supply: Regulator for Vproc of CPU cluster. + +Optional properties: +- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver + needs to do "voltage trace" to step by step scale up/down Vproc and + Vsram to fit SoC specific needs. When absent, the voltage scaling + flow is handled by hardware, hence no software "voltage trace" is + needed. +- #cooling-cells: +- cooling-min-level: +- cooling-max-level: + Please refer to Documentation/devicetree/bindings/thermal/thermal.txt. + +Example: +-------- + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x000>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&infracfg CLK_INFRA_CA53SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points = < + 507000 859000 + 702000 908000 + 1001000 983000 + 1105000 1009000 + 1183000 1028000 + 1404000 1083000 + 1508000 1109000 + 1573000 1125000 + >; + #cooling-cells = <2>; + cooling-min-level = <0>; + cooling-max-level = <7>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x001>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&infracfg CLK_INFRA_CA53SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points = < + 507000 859000 + 702000 908000 + 1001000 983000 + 1105000 1009000 + 1183000 1028000 + 1404000 1083000 + 1508000 1109000 + 1573000 1125000 + >; + #cooling-cells = <2>; + cooling-min-level = <0>; + cooling-max-level = <7>; + }; + + cpu2: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&infracfg CLK_INFRA_CA57SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points = < + 507000 828000 + 702000 867000 + 1001000 927000 + 1209000 968000 + 1404000 1007000 + 1612000 1049000 + 1807000 1089000 + 1989000 1125000 + >; + #cooling-cells = <2>; + cooling-min-level = <0>; + cooling-max-level = <7>; + }; + + cpu3: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&infracfg CLK_INFRA_CA57SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points = < + 507000 828000 + 702000 867000 + 1001000 927000 + 1209000 968000 + 1404000 1007000 + 1612000 1049000 + 1807000 1089000 + 1989000 1125000 + >; + #cooling-cells = <2>; + cooling-min-level = <0>; + cooling-max-level = <7>; + }; + + &cpu0 { + proc-supply = <&mt6397_vpca15_reg>; + }; + + &cpu1 { + proc-supply = <&mt6397_vpca15_reg>; + }; + + &cpu2 { + proc-supply = <&da9211_vcpu_reg>; + sram-supply = <&mt6397_vsramca7_reg>; + }; + + &cpu3 { + proc-supply = <&da9211_vcpu_reg>; + sram-supply = <&mt6397_vsramca7_reg>; + };