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[209.132.180.67]) by mx.google.com with ESMTP id gl5si4214294pbc.6.2015.03.23.22.49.49; Mon, 23 Mar 2015 22:49:51 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752268AbbCXFte (ORCPT + 27 others); Tue, 24 Mar 2015 01:49:34 -0400 Received: from mail-pd0-f172.google.com ([209.85.192.172]:36061 "EHLO mail-pd0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751275AbbCXFtd (ORCPT ); Tue, 24 Mar 2015 01:49:33 -0400 Received: by pdbcz9 with SMTP id cz9so210546037pdb.3 for ; Mon, 23 Mar 2015 22:49:32 -0700 (PDT) X-Received: by 10.68.194.137 with SMTP id hw9mr4666539pbc.162.1427176172426; Mon, 23 Mar 2015 22:49:32 -0700 (PDT) Received: from zcy-ubuntu.spreadtrum.com ([114.30.40.58]) by mx.google.com with ESMTPSA id ow2sm2874249pdb.14.2015.03.23.22.49.24 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Mar 2015 22:49:31 -0700 (PDT) From: Chunyan Zhang To: arm@kernel.org, arnd@arndb.de Cc: mathieu.poirier@linaro.org, will.deacon@arm.com, mark.rutland@arm.com, robh+dt@kernel.org, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, catalin.marinas@arm.com, kaixu.xia@linaro.org, zhizhou.zhang@spreadtrum.com, orsonzhai@gmail.com, zhang.lyra@gmail.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] coresight: adding basic support for Spreadtrum SC9836 Date: Tue, 24 Mar 2015 13:48:33 +0800 Message-Id: <1427176113-23411-1-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 1.9.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: zhang.chunyan@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.171 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Support only for ETB, FUNNEL, STM are included currently. Support for ETM, TPIU and the replicator linked to it are not included in this version patch. Signed-off-by: Chunyan Zhang --- arch/arm64/boot/dts/sprd/sc9836.dtsi | 57 ++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/sprd/sc9836.dtsi b/arch/arm64/boot/dts/sprd/sc9836.dtsi index f92f1b4..2ca80f3 100644 --- a/arch/arm64/boot/dts/sprd/sc9836.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9836.dtsi @@ -45,6 +45,63 @@ }; }; + etb@10003000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0 0x10003000 0 0x1000>; + arm,primecell-periphid = <0x0003b907>; + coresight-default-sink; + clocks = <&clk26mhz>; + clock-names = "apb_pclk"; + port { + etb_in: endpoint { + slave-mode; + remote-endpoint = <&funnel_out_port0>; + }; + }; + }; + + funnel@10001000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0x10001000 0 0x1000>; + clocks = <&clk26mhz>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* funnel output port */ + port@0 { + reg = <0>; + funnel_out_port0: endpoint { + remote-endpoint = <&etb_in>; + }; + }; + + /* funnel input port 0~3 is reserved for ETMs */ + port@1 { + reg = <4>; + funnel_in_port4: endpoint { + slave-mode; + remote-endpoint = <&stm_out>; + }; + }; + }; + }; + + stm@10006000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x10006000 0 0x1000>, + <0 0x01000000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + clocks = <&clk26mhz>; + clock-names = "apb_pclk"; + port { + stm_out: endpoint { + remote-endpoint = <&funnel_in_port4>; + }; + }; + }; + gic: interrupt-controller@12001000 { compatible = "arm,gic-400"; reg = <0 0x12001000 0 0x1000>,