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[209.132.180.67]) by mx.google.com with ESMTP id et2si40772652pbc.59.2014.09.18.10.15.58 for ; Thu, 18 Sep 2014 10:15:59 -0700 (PDT) Received-SPF: none (google.com: devicetree-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756669AbaIRRP5 (ORCPT + 5 others); Thu, 18 Sep 2014 13:15:57 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:54404 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756218AbaIRRP4 (ORCPT ); Thu, 18 Sep 2014 13:15:56 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s8IHFc1m020711; Thu, 18 Sep 2014 12:15:38 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s8IHFcoc004653; Thu, 18 Sep 2014 12:15:38 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Thu, 18 Sep 2014 12:15:38 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s8IHFb2P019997; Thu, 18 Sep 2014 12:15:37 -0500 From: Grygorii Strashko To: CC: , , Murali Karicheri , Grygorii Strashko Subject: [PATCH 3/3] ARM: dts: keystone: k2l: Fix chip selects for SPI devices Date: Thu, 18 Sep 2014 20:15:24 +0300 Message-ID: <1411060524-25077-4-git-send-email-grygorii.strashko@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1411060524-25077-1-git-send-email-grygorii.strashko@ti.com> References: <1411060524-25077-1-git-send-email-grygorii.strashko@ti.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.43 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Murali Karicheri There are 5 chip selects per SPI0 and SPI2 and 3 per SPI1. SPI2 needs to be pinned out to use and by default they are disabled. So keep the state disabled to reflect default. Signed-off-by: Murali Karicheri Signed-off-by: Grygorii Strashko --- arch/arm/boot/dts/k2l.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/k2l.dtsi b/arch/arm/boot/dts/k2l.dtsi index e3bb142..291db43 100644 --- a/arch/arm/boot/dts/k2l.dtsi +++ b/arch/arm/boot/dts/k2l.dtsi @@ -81,3 +81,17 @@ }; }; }; + +&spi0 { + ti,davinci-spi-num-cs = <5>; +}; + +&spi1 { + ti,davinci-spi-num-cs = <3>; +}; + +&spi2 { + ti,davinci-spi-num-cs = <5>; + /* Pin muxed. Enabled and configured by Bootloader */ + status = "disabled"; +};