From patchwork Thu Jul 17 09:00:42 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 33776 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wg0-f72.google.com (mail-wg0-f72.google.com [74.125.82.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 2992120969 for ; Thu, 17 Jul 2014 09:04:33 +0000 (UTC) Received: by mail-wg0-f72.google.com with SMTP id b13sf1622388wgh.3 for ; Thu, 17 Jul 2014 02:04:28 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe:content-type; bh=BGyPdGwCoFXoUZCGYse92xp23SGS7q6hfsGpqbjPjNQ=; b=YpTDmf903zCKXrW00pBVCvkneDY3oswbbO2c/4MhSxqaB4TIz9vaxiiy1j0OsT3wN/ oEWdR5dpeo+7LbsMOSU9Jbv3NYzcebSevaW3s4UBKWK3RbqX8VpU5Ml/LNPUbTatWUm/ 1Djj2eJ+nAlSTfQWu+pFZ92W0OHjlMVz/T0buPTwmau2khyjxxiOCLwREuhh1hYbT5wO oh4ICsmxX5iHYuDYGNc5Tsn0qiGX7fIV/7nt4aU1LgA9e97UWiS0VE/6hfRN7BJFF/7Q MZB9nsoBZ6XLnUSJyiXAioBz+zXAnyM3nLf6nv+esg+TCRbFniMwo7diOTwjMVWl5WRn /t6Q== X-Gm-Message-State: ALoCoQnG8bQ8OwoWty8V2urUjeycjJwAVBrHEqaLOY+hgikEp81e2GRzysXZhVhu9YT6e8z63OSw X-Received: by 10.180.208.37 with SMTP id mb5mr1860368wic.6.1405587867017; Thu, 17 Jul 2014 02:04:27 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.86.243 with SMTP id p106ls632597qgd.54.gmail; Thu, 17 Jul 2014 02:04:26 -0700 (PDT) X-Received: by 10.52.239.6 with SMTP id vo6mr13073780vdc.59.1405587866892; Thu, 17 Jul 2014 02:04:26 -0700 (PDT) Received: from mail-vc0-f180.google.com (mail-vc0-f180.google.com [209.85.220.180]) by mx.google.com with ESMTPS id t6si1561539vcr.86.2014.07.17.02.04.26 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 17 Jul 2014 02:04:26 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.180 as permitted sender) client-ip=209.85.220.180; Received: by mail-vc0-f180.google.com with SMTP id ij19so3995529vcb.11 for ; Thu, 17 Jul 2014 02:04:26 -0700 (PDT) X-Received: by 10.52.244.138 with SMTP id xg10mr13659020vdc.40.1405587866823; Thu, 17 Jul 2014 02:04:26 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.221.37.5 with SMTP id tc5csp18364vcb; Thu, 17 Jul 2014 02:04:26 -0700 (PDT) X-Received: by 10.70.15.133 with SMTP id x5mr515651pdc.163.1405587865916; Thu, 17 Jul 2014 02:04:25 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id sj7si1739268pbc.44.2014.07.17.02.04.25; Thu, 17 Jul 2014 02:04:25 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756369AbaGQJEL (ORCPT + 27 others); Thu, 17 Jul 2014 05:04:11 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:51487 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756015AbaGQJCX (ORCPT ); Thu, 17 Jul 2014 05:02:23 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id s6H91HlW021821; Thu, 17 Jul 2014 04:01:17 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6H91H7u015206; Thu, 17 Jul 2014 04:01:17 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.174.1; Thu, 17 Jul 2014 04:01:17 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6H9107h029985; Thu, 17 Jul 2014 04:01:13 -0500 From: Kishon Vijay Abraham I To: , , , , , , CC: , , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala Subject: [PATCH v3 3/4] Documentation: pci: ti: Add dt binding documentation for PCIe in DRA7xx Date: Thu, 17 Jul 2014 14:30:42 +0530 Message-ID: <1405587643-13808-4-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1405587643-13808-1-git-send-email-kishon@ti.com> References: <1405587643-13808-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: kishon@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.180 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Added dt binding documentation of PCIe in DRA7xx. Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: Bjorn Helgaas Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/pci/ti-pci.txt | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/ti-pci.txt diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt new file mode 100644 index 0000000..3d21791 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt @@ -0,0 +1,59 @@ +TI PCI Controllers + +PCIe Designware Controller + - compatible: Should be "ti,dra7-pcie"" + - reg : Two register ranges as listed in the reg-names property + - reg-names : The first entry must be "ti-conf" for the TI specific registers + The second entry must be "rc-dbics" for the designware pcie + registers + The third entry must be "config" for the PCIe configuration space + - phys : list of PHY specifiers (used by generic PHY framework) + - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the + number of PHYs as specified in *phys* property. + - ti,hwmods : Name of the hwmod associated to the pcie, "pcie", + where is the instance number of the pcie from the HW spec. + - interrupts : Two interrupt entries must be specified. The first one is for + main interrupt line and the second for MSI interrupt line. + - #address-cells, + #size-cells, + #interrupt-cells, + device_type, + ranges, + num-lanes, + interrupt-map-mask, + interrupt-map : as specified in ../designware-pcie.txt + +Example: +axi { + compatible = "simple-bus"; + #size-cells = <1>; + #address-cells = <1>; + ranges = <0x51000000 0x51000000 0x3000 + 0x0 0x20000000 0x10000000>; + pcie@51000000 { + compatible = "ti,dra7-pcie"; + reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; + reg-names = "rc_dbics", "ti_conf", "config"; + interrupts = <0 232 0x4>, <0 233 0x4>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x03000 0 0x00010000 + 0x82000000 0 0x20013000 0x13000 0 0xffed000>; + #interrupt-cells = <1>; + num-lanes = <1>; + ti,hwmods = "pcie1"; + phys = <&pcie1_phy>; + phy-names = "pcie-phy0"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 1>, + <0 0 0 2 &pcie_intc 2>, + <0 0 0 3 &pcie_intc 3>, + <0 0 0 4 &pcie_intc 4>; + pcie_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; +};