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[2001:770:15f::2]) by mx.google.com with ESMTPS id cm6si11681792wib.62.2014.02.18.03.49.06 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Feb 2014 03:49:07 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:770:15f::2 as permitted sender) client-ip=2001:770:15f::2; Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WFj9B-0002R5-5s; Tue, 18 Feb 2014 11:47:33 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WFj91-0007p9-Rf; Tue, 18 Feb 2014 11:47:23 +0000 Received: from service87.mimecast.com ([91.220.42.44]) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WFj8b-0007ka-Sk for linux-arm-kernel@lists.infradead.org; Tue, 18 Feb 2014 11:47:01 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Tue, 18 Feb 2014 11:46:32 +0000 Received: from red-moon.cambridge.arm.com ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 18 Feb 2014 11:46:31 +0000 From: Lorenzo Pieralisi To: devicetree@vger.kernel.org Subject: [PATCH RFC v4 2/3] Documentation: arm: add cache DT bindings Date: Tue, 18 Feb 2014 11:47:30 +0000 Message-Id: <1392724051-11950-3-git-send-email-lorenzo.pieralisi@arm.com> X-Mailer: git-send-email 1.8.4 In-Reply-To: <1392724051-11950-1-git-send-email-lorenzo.pieralisi@arm.com> References: <1392724051-11950-1-git-send-email-lorenzo.pieralisi@arm.com> X-OriginalArrivalTime: 18 Feb 2014 11:46:31.0805 (UTC) FILETIME=[1142DAD0:01CF2C9F] X-MC-Unique: 114021811463244001 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140218_064658_279555_C43882E1 X-CRM114-Status: GOOD ( 13.39 ) X-Spam-Score: 0.3 (/) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (0.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [91.220.42.44 listed in list.dnswl.org] 2.9 KHOP_BIG_TO_CC Sent to 10+ recipients instaed of Bcc or a list -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Mark Rutland , Mike Turquette , Tomasz Figa , Mark Hambleton , Lorenzo Pieralisi , Russell King , Sebastian Capella , Nicolas Pitre , Daniel Lezcano , linux-arm-kernel@lists.infradead.org, Grant Likely , Dave Martin , Charles Garcia Tobin , Kevin Hilman , linux-pm@vger.kernel.org, Kumar Gala , Rob Herring , Vincent Guittot , Antti Miettinen , Peter De Schrijver , Stephen Boyd , Amit Kucheria , Mark Brown , Santosh Shilimkar , Hanjun Guo , Sudeep Holla X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: lorenzo.pieralisi@arm.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.179 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 On ARM systems the cache topology cannot be probed at runtime, in particular, it is impossible to probe which CPUs share a given cache level. Power management software requires this knowledge to implement optimized power down sequences, hence this patch adds a document that defines the DT cache bindings for ARM systems. The bindings supersede cache bindings in the ePAPR (PowerPC bindings), because caches geometry for architected caches is probeable on ARM systems. This patch also adds properties that are specific to ARM architected caches to the existing ones defined in the ePAPR v1.1, as bindings extensions. Signed-off-by: Lorenzo Pieralisi --- Documentation/devicetree/bindings/arm/cache.txt | 167 +++++ 1 file changed, 167 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/cache.txt b/Documentation/devicetree/bindings/arm/cache.txt new file mode 100644 index 0000000..3af3d28 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cache.txt @@ -0,0 +1,167 @@ +========================================== +ARM processors cache binding description +========================================== + +Device tree bindings for cache nodes are already part of the ePAPR standard +v1.1 ([2]) for PowerPC platforms. This document defines the cache bindings +for caches on ARM processor systems. + +On ARM based systems most of the cache properties related to cache geometry +are probeable in HW (please refer to the processor TRMs in [1] for register +details), hence, unless otherwise stated, the properties defined in ePAPR for +internal, multi-level and shared caches ([2], 3.7.3, 3.8) are to be considered +superseded on ARM. + +On ARM, caches are either architected (directly controlled by the processor +through coprocessor instructions and tightly coupled with the processor +implementation) or unarchitected (controlled through a memory mapped +interface, implemented as a stand-alone IP external to the processor +implementation). + +This document provides the device tree bindings for ARM architected caches. + +- ARM architected cache node + + Description: must be a direct child of the cpu node. + A system can contain multiple architected cache nodes + per cpu node, linked through the next-level-cache phandle. + The next-level-cache property in the cpu node points to + the first level of architected cache for the CPU. + The next-level-cache links ordering must represent the + system cache hierarchy in the system, with the upper + cache level represented by a cache node with a missing + next-level-cache property. + + ARM architected cache node defines the following properties: + + - compatible + Usage: Required + Value type: + Definition: value shall be "arm,arch-cache". + + - power-domain + Usage: Optional + Value type: phandle + Definition: A phandle and power domain specifier as defined by + bindings of power domain specified by the + phandle [3]. + +Example(dual-cluster big.LITTLE system 32-bit) + + cpus { + #size-cells = <0>; + #address-cells = <1>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x0>; + next-level-cache = <&L1_0>; + + L1_0: l1-cache { + compatible = "arm,arch-cache"; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache { + compatible = "arm,arch-cache"; + }; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x1>; + next-level-cache = <&L1_1>; + + L1_1: l1-cache { + compatible = "arm,arch-cache"; + next-level-cache = <&L2_0>; + }; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x2>; + next-level-cache = <&L1_2>; + + L1_2: l1-cache { + compatible = "arm,arch-cache"; + next-level-cache = <&L2_0>; + }; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x3>; + next-level-cache = <&L1_3>; + + L1_3: l1-cache { + compatible = "arm,arch-cache"; + next-level-cache = <&L2_0>; + }; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + next-level-cache = <&L1_4>; + + L1_4: l1-cache { + compatible = "arm,arch-cache"; + next-level-cache = <&L2_1>; + }; + + L2_1: l2-cache { + compatible = "arm,arch-cache"; + }; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + next-level-cache = <&L1_5>; + + L1_5: l1-cache { + compatible = "arm,arch-cache"; + next-level-cache = <&L2_1>; + }; + }; + + cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x102>; + next-level-cache = <&L1_6>; + + L1_6: l1-cache { + compatible = "arm,arch-cache"; + next-level-cache = <&L2_1>; + }; + }; + + cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x103>; + next-level-cache = <&L1_7>; + + L1_7: l1-cache { + compatible = "arm,arch-cache"; + next-level-cache = <&L2_1>; + }; + }; + }; + +[1] ARM Architecture Reference Manuals + http://infocenter.arm.com/help/index.jsp + +[2] ePAPR standard + https://www.power.org/documentation/epapr-version-1-1/ + +[3] Kernel documentation - power domain bindings + Documentation/devicetree/bindings/power/power_domain.txt