From patchwork Thu Jul 8 15:50:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 471234 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp411688jao; Thu, 8 Jul 2021 08:50:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyOIdr+Yrf1A2cwbYI9GPR95P3/Qgem3Tt6VHXDNItPBb5XzjInyVr0wwTa5hj4kl1KZho8 X-Received: by 2002:aa7:d554:: with SMTP id u20mr39404772edr.50.1625759427146; Thu, 08 Jul 2021 08:50:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625759427; cv=none; d=google.com; s=arc-20160816; b=Q/r8mSv2DshYHrjU6l5pU4edCvFRnL5EJ4bFkDDd1zaSRXPPVJhWhxEpZYAUd3n3pm MlJOQZEuADCoPizlDLjnZ0TQe5DzxXX9gTpt8e9amFlSmMhqrLh+Yh1bgpqCGFWPsCC9 efxafcdb5pQqwtd2SjBoXAWgjiO5D44nLjm43EYM+ftQ63p1p4rqjad+4dHJ8GaPdYZ7 ET4sNNeVVxeTrC6R3BdzJ4ztBOiUtKQyRYzWm1/ClXL6OdJqrI9Q8itUNCvrWIroq2US c396KWkbRaADFuEeb+qhbAr+YB0pDA0lMtg2px/sg+TKpqJ5OJeKjrxf0l2Zemawzk8r Vjsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=BKzXSPmXRbbUAtxyh9kaeQW4inSE1gGtH1Hsu5BPnx4=; b=uUn1m2vukptiDhjO0dRXtQGh8hEdyM4i3H00T9IBacn2FubAh8oV/oBV41ZoG8Iloi hxe9/deGqnu9FqEM9CLHugGYW0pvpKAQW6FKveC3Ah9XEcekSi4eaBqUMdQpxVsQJLtS V9OlvtIlwjwKpGEYjlV0QUIEjc/Dwp6qmUK9VnfyfiQjXCyW5XU/AhUh1ocevpbgC6+P M0IyuvhxjMb23cFQ5rzSp0vrDcls9lt3q01QFZG99IwVKbRd76yEF4t3lTRa/znuPsiX bl91A6vIvR6tesZ8A6L7JNqv/eCrYG6sZfpfU3ZRe9fP8z89W2dFAEJTU2BvfRC3SvTg J19A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b="b/Ch39fI"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id dq22si3171093ejc.51.2021.07.08.08.50.26; Thu, 08 Jul 2021 08:50:27 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b="b/Ch39fI"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232098AbhGHPxG (ORCPT + 7 others); Thu, 8 Jul 2021 11:53:06 -0400 Received: from mail.kernel.org ([198.145.29.99]:59334 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231896AbhGHPxF (ORCPT ); Thu, 8 Jul 2021 11:53:05 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 9021461624; Thu, 8 Jul 2021 15:50:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1625759423; bh=oO0TJE2ebCH2U3v7nqyP0JF2DLGm9sfIIPwwlL+As0g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=b/Ch39fI+CWuV4Yu9mq3tzNUYHaLEVSf9JtJZH1R9/ZaW7vTBLy7gCinrIW7Wtr1w QYT0cCJKBjWPqQ1zXzqgxSvMt4fHT9Uh8FcFc+05JAPWgBu6jwuEG3SLihiLSoO8wK eNQGJB0STWx0m9a6vyuKVPH5+H/9H+bcv1/srzBHFwZt1+cyhdzFWzLnDVEBFIjxqO mG9dL17zEmVogKjj03D2WikhOgyR6Us53SCWUGIVbuAALKdbp1+1L0TgF3CnjHlHfA 8L244kX5goXAkif2ve1l8x5G4+x1oknGxDknF9Ol83sNAT1h69KPL4dX+soqYImlb7 Q7mrmMFToeiyA== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1m1WI4-008VVL-Lc; Thu, 08 Jul 2021 17:50:16 +0200 From: Mauro Carvalho Chehab To: Manivannan Sadhasivam , Rob Herring Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Manivannan Sadhasivam , Rob Herring , Wei Xu , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mauro Carvalho Chehab Subject: [PATCH RFC 7/7] arm64: dts: hisilicon: Add support for HiKey 970 PCIe controller hardware Date: Thu, 8 Jul 2021 17:50:14 +0200 Message-Id: <00f9c0f215308629bc6a91682f3dcf528b351a7a.1625758732.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Manivannan Sadhasivam Add DTS bindings for the Hikey 970 board's PCIe hardware. [mchehab+huawei@kernel.org: fix merge conflicts] Signed-off-by: Manivannan Sadhasivam Signed-off-by: Mauro Carvalho Chehab --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 72 +++++++++++++++++++ .../boot/dts/hisilicon/hikey970-pmic.dtsi | 1 - 2 files changed, 72 insertions(+), 1 deletion(-) -- 2.31.1 diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 6476149d99e3..0fbc1f2ac599 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -177,6 +177,12 @@ sctrl: sctrl@fff0a000 { #clock-cells = <1>; }; + pmctrl: pmctrl@fff31000 { + compatible = "hisilicon,hi3670-pmctrl", "syscon"; + reg = <0x0 0xfff31000 0x0 0x1000>; + #clock-cells = <1>; + }; + iomcu: iomcu@ffd7e000 { compatible = "hisilicon,hi3670-iomcu", "syscon"; reg = <0x0 0xffd7e000 0x0 0x1000>; @@ -660,6 +666,72 @@ gpio28: gpio@fff1d000 { clock-names = "apb_pclk"; }; + its_pcie: interrupt-controller@f4000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0xf5100000 0x0 0x100000>; + }; + + pcie_phy: pcie-phy@fc000000 { + compatible = "hisilicon,hi970-pcie-phy"; + reg = <0x0 0xfc000000 0x0 0x80000>; + reg-names = "phy"; + + phy-supply = <&ldo33>; + + clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3670_ACLK_GATE_PCIE>; + + clock-names = "pcie_phy_ref", "pcie_apb_phy", + "pcie_aclk"; + + reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >, + <&gpio3 1 0 >, <&gpio27 4 0 >; + + clkreq-gpios = <&gpio20 6 0 >, <&gpio27 3 0 >, + <&gpio17 0 0 >; + + /* vboost iboost pre post main */ + eye_param = <0xFFFFFFFF 0xFFFFFFFF + 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF>; + + #phy-cells = <0>; + }; + + pcie@f4000000 { + compatible = "hisilicon,kirin970-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000000>, + <0x0 0xfc180000 0x0 0x1000>, + <0x0 0xf5000000 0x0 0x2000>; + reg-names = "dbi", "apb", "config"; + bus-range = <0x0 0x1>; + msi-parent = <&its_pcie>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + phys = <&pcie_phy>; + ranges = <0x02000000 0x0 0x00000000 + 0x0 0xf6000000 + 0x0 0x02000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupts = <0 283 4>; + interrupt-names = "msi"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0x0 0 0 1 + &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 2 + &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 3 + &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 4 + &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>; + clock-names = "pcie_aux", "pcie_apb_sys"; + }; + /* UFS */ ufs: ufs@ff3c0000 { compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1"; diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi index 48c739eacba0..03452e627641 100644 --- a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi @@ -73,7 +73,6 @@ ldo33: LDO33 { /* PEX8606 */ regulator-name = "ldo33"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <3300000>; - regulator-boot-on; }; ldo34: LDO34 { /* GPS AUX IN VDD */