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PHY: Add support for SERDES in TI's J721E SoC
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No
| 7 patches
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andy.doan@linaro.org
andy.doan@linaro.org
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[v4,13/14] dt-bindings: phy: Document WIZ (SERDES wrapper) bindings
PHY: Add support for SERDES in TI's J721E SoC
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2019-12-16
Kishon Vijay Abraham I
Accepted
[v4,10/14] phy: cadence: Sierra: Change MAX_LANES of Sierra to 16
PHY: Add support for SERDES in TI's J721E SoC
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2019-12-16
Kishon Vijay Abraham I
Accepted
[v4,09/14] phy: cadence: Sierra: Check for PLL lock during PHY power on
PHY: Add support for SERDES in TI's J721E SoC
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2019-12-16
Kishon Vijay Abraham I
Accepted
[v4,08/14] phy: cadence: Sierra: Get reset control "array" for each link
PHY: Add support for SERDES in TI's J721E SoC
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2019-12-16
Kishon Vijay Abraham I
New
[v4,07/14] phy: cadence: Sierra: Configure both lane cdb and common cdb registers for external SSC
PHY: Add support for SERDES in TI's J721E SoC
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2019-12-16
Kishon Vijay Abraham I
Accepted
[v4,04/14] phy: cadence: Sierra: Add support for SERDES_16G used in J721E SoC
PHY: Add support for SERDES in TI's J721E SoC
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2019-12-16
Kishon Vijay Abraham I
Accepted
[v4,01/14] dt-bindings: phy: Sierra: Add bindings for Sierra in TI's J721E
PHY: Add support for SERDES in TI's J721E SoC
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2019-12-16
Kishon Vijay Abraham I
Accepted