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Add non-coherent DMA support for AX45MP
| Archived =
No
| 3 patches
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andy.doan@linaro.org
andy.doan@linaro.org
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[v10,5/6] cache: Add L2 cache management for Andes AX45MP RISC-V core
Add non-coherent DMA support for AX45MP
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2023-07-02
Lad, Prabhakar
Superseded
[v10,4/6] dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller
Add non-coherent DMA support for AX45MP
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-
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2023-07-02
Lad, Prabhakar
Superseded
[v10,2/6] riscv: errata: Add Andes alternative ports
Add non-coherent DMA support for AX45MP
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2023-07-02
Lad, Prabhakar
New