Toggle navigation
Patchwork
devicetree
Patches
Bundles
About this project
Login
Register
Mail settings
Show patches with
: Series =
RISC-V non-coherent function pointer based cache management operations + non-coherent DMA support for AX45MP
| Archived =
No
| 6 patches
Series
Submitter
State
any
Action Required
New
Under Review
Accepted
Rejected
RFC
Not Applicable
Changes Requested
Awaiting Upstream
Superseded
Deferred
Search
Archived
No
Yes
Both
Delegate
------
Nobody
andy.doan@linaro.org
andy.doan@linaro.org
Apply
Patch
Series
S/W/F
Date
Submitter
Delegate
State
[v6,6/6] soc: renesas: Kconfig: Select the required configs for RZ/Five SoC
RISC-V non-coherent function pointer based cache management operations + non-coherent DMA support...
-
-
-
2023-01-06
Lad, Prabhakar
Superseded
[v6,5/6] cache: Add L2 cache management for Andes AX45MP RISC-V core
RISC-V non-coherent function pointer based cache management operations + non-coherent DMA support...
-
-
-
2023-01-06
Lad, Prabhakar
New
[v6,4/6] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller
RISC-V non-coherent function pointer based cache management operations + non-coherent DMA support...
-
-
-
2023-01-06
Lad, Prabhakar
Superseded
[v6,3/6] riscv: errata: Add Andes alternative ports
RISC-V non-coherent function pointer based cache management operations + non-coherent DMA support...
-
-
-
2023-01-06
Lad, Prabhakar
Superseded
[v6,2/6] riscv: asm: vendorid_list: Add Andes Technology to the vendors list
RISC-V non-coherent function pointer based cache management operations + non-coherent DMA support...
-
-
-
2023-01-06
Lad, Prabhakar
Superseded
[RFC,v6,1/6] riscv: mm: dma-noncoherent: Switch using function pointers for cache management
RISC-V non-coherent function pointer based cache management operations + non-coherent DMA support...
-
-
-
2023-01-06
Lad, Prabhakar
New