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Thu, 7 Dec 2023 08:36:18 +0000 Received: from IA1PR20MB4953.namprd20.prod.outlook.com ([fe80::55b:c350:980:ad8]) by IA1PR20MB4953.namprd20.prod.outlook.com ([fe80::55b:c350:980:ad8%6]) with mapi id 15.20.7046.024; Thu, 7 Dec 2023 08:36:18 +0000 From: Inochi Amaoto To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chao Wei , Chen Wang , Paul Walmsley , Palmer Dabbelt , Albert Ou , Inochi Amaoto Cc: Jisheng Zhang , Liu Gui , Emil Renner Berthing , qiujingbao.dlmu@gmail.com, dlan@gentoo.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 0/4] riscv: sophgo: add clock support for Sophgo CV1800 SoCs Date: Thu, 7 Dec 2023 16:36:17 +0800 Message-ID: X-Mailer: git-send-email 2.43.0 X-TMN: [G/eCHKOyduTaY5FL1jADlOLE/LlZEEuEsS93U/nOd58=] X-ClientProxiedBy: TYCP286CA0341.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:38e::9) To IA1PR20MB4953.namprd20.prod.outlook.com (2603:10b6:208:3af::19) X-Microsoft-Original-Message-ID: <20231207083618.872121-1-inochiama@outlook.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: IA1PR20MB4953:EE_|LV2PR20MB4582:EE_ X-MS-Office365-Filtering-Correlation-Id: 21e5ed8d-2ec1-4eef-d726-08dbf6ff9529 X-Microsoft-Antispam: BCL:0; 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This patch follow this patch series: https://lore.kernel.org/all/IA1PR20MB495399CAF2EEECC206ADA7ABBBD5A@IA1PR20MB4953.namprd20.prod.outlook.com/ Changed from v2: 1. remove clock-names from bindings. 2. remove clock-frequency node of DT from previous patch. 3. change some unused clock to bypass mode to avoid unlockable PLL. Changed from v1: 1. fix license issues. Inochi Amaoto (4): dt-bindings: clock: sophgo: Add clock controller of CV1800 series SoC clk: sophgo: Add CV1800 series clock controller driver riscv: dts: sophgo: add clock generator for Sophgo CV1800 series SoC riscv: dts: sophgo: add uart clock for Sophgo CV1800 series SoC .../bindings/clock/sophgo,cv1800-clk.yaml | 46 + arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 4 + arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 4 + arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 22 +- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/sophgo/Kconfig | 12 + drivers/clk/sophgo/Makefile | 7 + drivers/clk/sophgo/clk-cv1800.c | 1574 +++++++++++++++++ drivers/clk/sophgo/clk-cv1800.h | 123 ++ drivers/clk/sophgo/clk-cv18xx-common.c | 76 + drivers/clk/sophgo/clk-cv18xx-common.h | 85 + drivers/clk/sophgo/clk-cv18xx-ip.c | 894 ++++++++++ drivers/clk/sophgo/clk-cv18xx-ip.h | 266 +++ drivers/clk/sophgo/clk-cv18xx-pll.c | 465 +++++ drivers/clk/sophgo/clk-cv18xx-pll.h | 79 + include/dt-bindings/clock/sophgo,cv1800.h | 176 ++ 17 files changed, 3830 insertions(+), 5 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/sophgo,cv1800-clk.yaml create mode 100644 drivers/clk/sophgo/Kconfig create mode 100644 drivers/clk/sophgo/Makefile create mode 100644 drivers/clk/sophgo/clk-cv1800.c create mode 100644 drivers/clk/sophgo/clk-cv1800.h create mode 100644 drivers/clk/sophgo/clk-cv18xx-common.c create mode 100644 drivers/clk/sophgo/clk-cv18xx-common.h create mode 100644 drivers/clk/sophgo/clk-cv18xx-ip.c create mode 100644 drivers/clk/sophgo/clk-cv18xx-ip.h create mode 100644 drivers/clk/sophgo/clk-cv18xx-pll.c create mode 100644 drivers/clk/sophgo/clk-cv18xx-pll.h create mode 100644 include/dt-bindings/clock/sophgo,cv1800.h --- 2.43.0