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[v3,0/5] PHY: Add support for dual refclk configurations in Cadence Torrent PHY driver

Message ID 20231221162051.2131202-1-sjakhade@cadence.com
Headers show
Series PHY: Add support for dual refclk configurations in Cadence Torrent PHY driver | expand

Message

Swapnil Jakhade Dec. 21, 2023, 4:20 p.m. UTC 
This patch series extends Torrent PHY driver functionality to support
dual input reference clocks.

It also adds support for following multilink configurations:
- PCIe(100MHz) + USXGMII(156.25MHz)
- USXGMII(156.25MHz) + SGMII/QSGMII(100MHz)

The changes have been validated on TI J721E and J7200 platforms.

v1 of the patch series can be found at [1].

Version History:

v3:
   - Updated clock description in DT documentation
   - Added Acked-by from Conor

v2:
   - Rename refclk1 to pll1_refclk in bindings and in driver
   - Simplify clock-names as suggested by Rob

[1] https://lore.kernel.org/linux-phy/20230724150002.5645-1-sjakhade@cadence.com/

Swapnil Jakhade (5):
  dt-bindings: phy: cadence-torrent: Add optional input reference clock
    for PLL1
  phy: cadence-torrent: Add PCIe(100MHz) + USXGMII(156.25MHz) multilink
    configuration
  phy: cadence-torrent: Add USXGMII(156.25MHz) + SGMII/QSGMII(100MHz)
    multilink configuration
  dt-bindings: phy: cadence-torrent: Add a separate compatible for TI
    J7200
  phy: cadence-torrent: Add USXGMII(156.25MHz) + SGMII/QSGMII(100MHz)
    multilink config for TI J7200

 .../bindings/phy/phy-cadence-torrent.yaml     |  11 +-
 drivers/phy/cadence/phy-cadence-torrent.c     | 705 +++++++++++++++++-
 2 files changed, 710 insertions(+), 6 deletions(-)

Comments

Krzysztof Kozlowski Dec. 21, 2023, 8:35 p.m. UTC | #1 
On 21/12/2023 17:20, Swapnil Jakhade wrote:
> Add a new optional input reference clock (pll1_refclk) for PLL1.
> Update bindings to support dual reference clock multilink configurations.
> 
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof
Roger Quadros Dec. 22, 2023, 10:11 a.m. UTC | #2 
On 21/12/2023 18:20, Swapnil Jakhade wrote:
> Add a separate compatible and registers map table for TI J7200.
> TI J7200 uses Torrent SD0805 version which is a special version
> derived from Torrent SD0801 with some differences in register
> configurations.
> 
> Add register sequences for USXGMII(156.25MHz) + SGMII/QSGMII(100MHz)
> multilink config for TI J7200. USXGMII uses PLL0 and SGMII/QSGMII
> uses PLL1.
> 
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>

Reviewed-by: Roger Quadros <rogerq@kernel.org>