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[178.235.179.137]) by smtp.gmail.com with ESMTPSA id ts7-20020a170907c5c700b00a1dd58874b8sm14260693ejc.119.2023.12.18.08.02.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 08:02:14 -0800 (PST) From: Konrad Dybcio Subject: [PATCH 00/12] 8550 fixups Date: Mon, 18 Dec 2023 17:02:01 +0100 Message-Id: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAPlsgGUC/x2L0QqDMAwAf0XyvICtOMRfERltms6AVGl0DMR/X 9jjHXcXKFdhhbG5oPJHVLZi4B4N0BLKm1GSMfjWd867AY9tF8Kh79tXli8r+kjPjlJmlxPYFoM yxhoKLTaWc11N7pX/tZlpvu8fJCfhincAAAA= To: Bjorn Andersson , Georgi Djakov , Abel Vesa , Michael Turquette , Stephen Boyd , Taniya Das , Jagadeesh Kona , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sai Prakash Ranjan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1702915332; l=1669; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=6Yb6Qe/+BKF3DV+Lv1BhKuTvaTNyVIFwB8H4W5q8BdI=; b=WN6C/G5NMRK0U5PRvi6RcGbFHGJhOq0WE7mMSQzhNKn7wyhSth6m02iTHjs3EDXx7AmQreUZ+ qE3T1qxAX9ED17zx28TncGmUEfwG8aEyZttWnxMiImBy7buOGhSsja0 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= I found a couple of sneaky bugs concerning 8550, ranging from icc and clk, to some usual omissions in the dts. This series attempts to amend them to mostly prevent UB due to misconfiguration. Patches 1-2 for icc, rest for qcom Signed-off-by: Konrad Dybcio --- Konrad Dybcio (12): interconnect: qcom: sm8550: Remove bogus per-RSC BCMs and nodes interconnect: qcom: sm8550: Enable sync_state clk: qcom: gcc-sm8550: Add the missing RETAIN_FF_ENABLE GDSC flag clk: qcom: gcc-sm8550: Mark the PCIe GDSCs votable clk: qcom: gcc-sm8550: use collapse-voting for PCIe GDSCs clk: qcom: gcc-sm8550: Mark RCGs shared where applicable clk: qcom: gpucc-sm8550: Update GPU PLL settings clk: qcom: dispcc-sm8550: Update disp PLL settings clk: qcom: dispcc-sm8550: Use the correct PLL configuration function arm64: dts: qcom: sm8550: Switch UFS from opp-table-hz to opp-v2 arm64: dts: qcom: sm8550: Separate out X3 idle state arm64: dts: qcom: sm8550: Update idle state time requirements arch/arm64/boot/dts/qcom/sm8550.dtsi | 82 +++-- drivers/clk/qcom/dispcc-sm8550.c | 12 +- drivers/clk/qcom/gcc-sm8550.c | 110 +++---- drivers/clk/qcom/gpucc-sm8550.c | 6 +- drivers/interconnect/qcom/sm8550.c | 575 +---------------------------------- drivers/interconnect/qcom/sm8550.h | 284 ++++++++--------- 6 files changed, 257 insertions(+), 812 deletions(-) --- base-commit: ceb2fe0d438644e1de06b9a6468a1fb8e2199c70 change-id: 20231218-topic-8550_fixes-2bc63cdfe1fd Best regards,