From patchwork Wed Nov 22 15:42:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 746157 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="mji1BkSe" Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD1FF1722; Wed, 22 Nov 2023 07:42:53 -0800 (PST) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3AMFgkoF031020; Wed, 22 Nov 2023 09:42:46 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1700667766; bh=DLJe1Pv87UHy4+v/+5Kl00sc0UqsngVKRFxbrZDoRBc=; h=From:To:CC:Subject:Date; b=mji1BkSeSk8jptEDhZpS9TG7R2mKKMR2VLHw0WFskUBSkNtKuiospkQSzYFuezXWv maYIxJIFzleiV9fuBCC5pEkWrgABRPWkz6qWW7MOcMzn2iRLlZjOJzd3PQs+mA3VPR 7xjLF7FsySaoedySQEEVOP/Dizw3LS6+/GpDLbk8= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3AMFgkMn011949 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 22 Nov 2023 09:42:46 -0600 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 22 Nov 2023 09:42:45 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 22 Nov 2023 09:42:45 -0600 Received: from uda0132425.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3AMFggJl046973; Wed, 22 Nov 2023 09:42:43 -0600 From: Vignesh Raghavendra To: Peter Ujfalusi , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Vignesh Raghavendra , Subject: [PATCH v2 0/4] dt-bindings: dma: ti: k3*: Update optional reg regions Date: Wed, 22 Nov 2023 21:12:34 +0530 Message-ID: <20231122154238.815781-1-vigneshr@ti.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 DMAs on TI K3 SoCs have channel configuration registers region which are usually hidden from Linux and configured via Device Manager Firmware APIs. But certain early SWs like bootloader which run before Device Manager is fully up would need to directly configure these registers and thus require to be in DT description. This add bindings for such configuration regions. Backward compatibility is maintained to existing DT by only mandating existing regions to be present and this new region as optional. This update is mainly to aid SPL/U-Boot to reuse kernel DT as is. And is applicable to entire K3 family of SoCs. v2: Fix issues pointed out by Conor and Peter * Add new patch 1/4 to describe existing register regions * Rename cfg region as ring * Add bchan register space for bcdma * Include descriptions for new registers v1: https://lore.kernel.org/all/20230810174356.3322583-1-vigneshr@ti.com/ Vignesh Raghavendra (4): dt-bindings: dma: ti: k3-*: Add descriptions for register regions dt-bindings: dma: ti: k3-bcdma: Describe cfg register regions dt-bindings: dma: ti: k3-pktdma: Describe cfg register regions dt-bindings: dma: ti: k3-udma: Describe cfg register regions .../devicetree/bindings/dma/ti/k3-bcdma.yaml | 43 +++++++++++++------ .../devicetree/bindings/dma/ti/k3-pktdma.yaml | 26 +++++++++-- .../devicetree/bindings/dma/ti/k3-udma.yaml | 20 +++++++-- 3 files changed, 71 insertions(+), 18 deletions(-)