| Message ID | 20231122141426.329694-1-paul.kocialkowski@bootlin.com |
|---|---|
| Headers | show |
| Series | Allwinner A31/A83T MIPI CSI-2 and A31 ISP / Platform Support | expand |
Hi Paul! Sorry for late reply. On Wednesday, November 22, 2023 3:14:21 PM CET Paul Kocialkowski wrote: > MIPI CSI-2 is supported on the V3s with an A31-based MIPI CSI-2 bridge > controller. The controller uses a separate D-PHY, which is the same > that is otherwise used for MIPI DSI, but used in Rx mode. > > On the V3s, the CSI0 controller is dedicated to MIPI CSI-2 as it does > not have access to any parallel interface pins. > > Add all the necessary nodes (CSI0, MIPI CSI-2 bridge and D-PHY) to > support the MIPI CSI-2 interface. > > Note that a fwnode graph link is created between CSI0 and MIPI CSI-2 > even when no sensor is connected. This will result in a probe failure > for the controller as long as no sensor is connected but this is fine > since no other interface is available. > > The interconnects property is used to inherit the proper DMA offset. > > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> > --- > arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 71 ++++++++++++++++++++++ > 1 file changed, 71 insertions(+) > > diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi > index 506e98f4f69d..d57612023aa4 100644 > --- a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi > +++ b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi > @@ -621,6 +621,77 @@ gic: interrupt-controller@1c81000 { > interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > }; > > + csi0: camera@1cb0000 { > + compatible = "allwinner,sun8i-v3s-csi"; > + reg = <0x01cb0000 0x1000>; > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_CSI>, > + <&ccu CLK_CSI1_SCLK>, > + <&ccu CLK_DRAM_CSI>; > + clock-names = "bus", "mod", "ram"; > + resets = <&ccu RST_BUS_CSI>; > + interconnects = <&mbus 5>; > + interconnect-names = "dma-mem"; As far as I can see, interconnects are not documented in allwinner,sun6i-a31-csi.yaml. Please run make dtbs_check on this. Best regards, Jernej > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@1 { > + reg = <1>; > + > + csi0_in_mipi_csi2: endpoint { > + remote-endpoint = <&mipi_csi2_out_csi0>; > + }; > + }; > + }; > + }; > + > + mipi_csi2: csi@1cb1000 { > + compatible = "allwinner,sun8i-v3s-mipi-csi2", > + "allwinner,sun6i-a31-mipi-csi2"; > + reg = <0x01cb1000 0x1000>; > + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_CSI>, > + <&ccu CLK_CSI1_SCLK>; > + clock-names = "bus", "mod"; > + resets = <&ccu RST_BUS_CSI>; > + status = "disabled"; > + > + phys = <&dphy>; > + phy-names = "dphy"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + mipi_csi2_in: port@0 { > + reg = <0>; > + }; > + > + mipi_csi2_out: port@1 { > + reg = <1>; > + > + mipi_csi2_out_csi0: endpoint { > + remote-endpoint = <&csi0_in_mipi_csi2>; > + }; > + }; > + }; > + }; > + > + dphy: d-phy@1cb2000 { > + compatible = "allwinner,sun6i-a31-mipi-dphy"; > + reg = <0x01cb2000 0x1000>; > + clocks = <&ccu CLK_BUS_CSI>, > + <&ccu CLK_MIPI_CSI>; > + clock-names = "bus", "mod"; > + resets = <&ccu RST_BUS_CSI>; > + allwinner,direction = "rx"; > + status = "disabled"; > + #phy-cells = <0>; > + }; > + > csi1: camera@1cb4000 { > compatible = "allwinner,sun8i-v3s-csi"; > reg = <0x01cb4000 0x3000>; >
On Wednesday, November 22, 2023 3:14:23 PM CET Paul Kocialkowski wrote: > MIPI CSI-2 is supported on the A83T with a dedicated controller that > covers both the protocol and D-PHY. It is connected to the only CSI > receiver with a fwnode graph link. Note that the CSI receiver supports > both this MIPI CSI-2 source and a parallel source. > > An empty port with a label for the MIPI CSI-2 sensor input is also > defined for convenience. > > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Best regards, Jernej > --- > arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 43 +++++++++++++++++++++ > 1 file changed, 43 insertions(+) > > diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi > index 94eb3bfc989e..b74c3f9e6598 100644 > --- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi > +++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi > @@ -1062,6 +1062,49 @@ csi: camera@1cb0000 { > clock-names = "bus", "mod", "ram"; > resets = <&ccu RST_BUS_CSI>; > status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@1 { > + reg = <1>; > + > + csi_in_mipi_csi2: endpoint { > + remote-endpoint = <&mipi_csi2_out_csi>; > + }; > + }; > + }; > + }; > + > + mipi_csi2: csi@1cb1000 { > + compatible = "allwinner,sun8i-a83t-mipi-csi2"; > + reg = <0x01cb1000 0x1000>; > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_CSI>, > + <&ccu CLK_CSI_SCLK>, > + <&ccu CLK_MIPI_CSI>, > + <&ccu CLK_CSI_MISC>; > + clock-names = "bus", "mod", "mipi", "misc"; > + resets = <&ccu RST_BUS_CSI>; > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + mipi_csi2_in: port@0 { > + reg = <0>; > + }; > + > + mipi_csi2_out: port@1 { > + reg = <1>; > + > + mipi_csi2_out_csi: endpoint { > + remote-endpoint = <&csi_in_mipi_csi2>; > + }; > + }; > + }; > }; > > hdmi: hdmi@1ee0000 { >