From patchwork Mon Nov 6 08:55:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xianwei Zhao X-Patchwork-Id: 742077 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8AE27111A5 for ; Mon, 6 Nov 2023 08:56:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=none Received: from mail-sh.amlogic.com (mail-sh.amlogic.com [58.32.228.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D66F83; Mon, 6 Nov 2023 00:56:02 -0800 (PST) Received: from droid01-cd.amlogic.com (10.98.11.200) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.13; Mon, 6 Nov 2023 16:55:59 +0800 From: Xianwei Zhao To: , , , , CC: Neil Armstrong , Jerome Brunet , Michael Turquette , "Stephen Boyd" , Rob Herring , "Krzysztof Kozlowski" , Kevin Hilman , Martin Blumenstingl , Chuan Liu , Xianwei Zhao Subject: [PATCH V6 0/4] Add C3 SoC PLLs and Peripheral clock Date: Mon, 6 Nov 2023 16:55:50 +0800 Message-ID: <20231106085554.3237511-1-xianwei.zhao@amlogic.com> X-Mailer: git-send-email 2.37.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.98.11.200] The patchset adds support for the peripheral and PLL clock controller found on the Amlogic C3 SoC family, such as C302X or C308L. Changes since V5 [3]: - Fix some typo and modify formart for MARCO. Suggested by Jerome. - Add pad clock for peripheral input clock in bindings. - Add some description for explaining why ddr_dpll_pt_clk and cts_msr_clk are out of tree. Changes since V4 [10]: - Change some fw_name of clocks. Suggested by Jerome. - Delete minItem of clocks. - Add CLk_GET_RATE_NOCACHE flags for gp1_pll - Fix some format. and fix width as 8 for mclk_pll_dco. - exchange gate and divder for fclk_50m clock. - add CLK_SET_RATE_PARENT for axi_a_divder & axi_b_divder. - add CLK_IS_CRITICAL for axi_clk - Optimized macro define for pwm clk. - add cts_oscin_clk mux between 24M and 32k - add some missing gate clock, such as ddr_pll. Changes since V3 [7]: - Modify Kconfig desc and PLL yaml clk desc. - Fix some format.Suggested by Yixun and Jerome. - Add flag CLK_GET_RATE_NOCACHE for sys_clk. - Optimized macro define for pwm clk. - Use flag CLK_IS_CRITICAL for axi_clk. - Add some description for some clocks. - Use FCLK_50M instead of FCLK_DIV40. Changes since V2 [4]: - Modify some format, include clk name & inline, and so on. - Define marco for pwm clock. - Add GP1_PLL clock. - Modify yaml use raw instead of macro. Changes since V1 [2]: - Fix errors when check binding by using "make dt_binding_check". - Delete macro definition. Xianwei Zhao (4): dt-bindings: clock: add Amlogic C3 PLL clock controller bindings dt-bindings: clock: add Amlogic C3 peripherals clock controller bindings clk: meson: c3: add support for the C3 SoC PLL clock clk: meson: c3: add c3 clock peripherals controller driver .../clock/amlogic,c3-peripherals-clkc.yaml | 104 + .../bindings/clock/amlogic,c3-pll-clkc.yaml | 59 + drivers/clk/meson/Kconfig | 26 + drivers/clk/meson/Makefile | 2 + drivers/clk/meson/c3-peripherals.c | 2745 +++++++++++++++++ drivers/clk/meson/c3-pll.c | 895 ++++++ .../clock/amlogic,c3-peripherals-clkc.h | 237 ++ .../dt-bindings/clock/amlogic,c3-pll-clkc.h | 44 + 8 files changed, 4112 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,c3-peripherals-clkc.yaml create mode 100644 Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml create mode 100644 drivers/clk/meson/c3-peripherals.c create mode 100644 drivers/clk/meson/c3-pll.c create mode 100644 include/dt-bindings/clock/amlogic,c3-peripherals-clkc.h create mode 100644 include/dt-bindings/clock/amlogic,c3-pll-clkc.h base-commit: 57b55c76aaf1ba50ecc6dcee5cd6843dc4d85239 Reviewed-by: Krzysztof Kozlowski