From patchwork Tue Oct 10 06:29:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xianwei Zhao X-Patchwork-Id: 731593 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD05FA55 for ; Tue, 10 Oct 2023 06:29:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=none Received: from mail-sh.amlogic.com (mail-sh.amlogic.com [58.32.228.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F3FF5B7; Mon, 9 Oct 2023 23:29:31 -0700 (PDT) Received: from droid01-cd.amlogic.com (10.98.11.200) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.13; Tue, 10 Oct 2023 14:29:19 +0800 From: Xianwei Zhao To: , , , , CC: Neil Armstrong , Jerome Brunet , Michael Turquette , "Stephen Boyd" , Rob Herring , "Krzysztof Kozlowski" , Kevin Hilman , Martin Blumenstingl , Chuan Liu , Xianwei Zhao Subject: [PATCH V2 0/4] Add C3 SoC PLLs and Peripheral clock Date: Tue, 10 Oct 2023 14:29:13 +0800 Message-ID: <20231010062917.3624223-1-xianwei.zhao@amlogic.com> X-Mailer: git-send-email 2.37.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.98.11.200] X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Add C3 SoC PLLs and Peripheral clock controller dt-bindings. Add PLLs and Peripheral clock controller driver for C3 SOC. V1 -> V2: 1. Fix errors when check binding by using "make dt_binding_check" 2. Delete macro definition Xianwei Zhao (4): dt-bindings: clock: add Amlogic C3 PLL clock controller bindings dt-bindings: clock: add Amlogic C3 peripherals clock controller bindings clk: meson: c3: add support for the C3 SoC PLL clock clk: meson: c3: add c3 clock peripherals controller driver .../clock/amlogic,c3-peripherals-clkc.yaml | 92 + .../bindings/clock/amlogic,c3-pll-clkc.yaml | 59 + drivers/clk/meson/Kconfig | 25 + drivers/clk/meson/Makefile | 2 + drivers/clk/meson/c3-peripherals.c | 3096 +++++++++++++++++ drivers/clk/meson/c3-peripherals.h | 48 + drivers/clk/meson/c3-pll.c | 808 +++++ drivers/clk/meson/c3-pll.h | 35 + .../clock/amlogic,c3-peripherals-clkc.h | 230 ++ .../dt-bindings/clock/amlogic,c3-pll-clkc.h | 42 + 10 files changed, 4437 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,c3-peripherals-clkc.yaml create mode 100644 Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml create mode 100644 drivers/clk/meson/c3-peripherals.c create mode 100644 drivers/clk/meson/c3-peripherals.h create mode 100644 drivers/clk/meson/c3-pll.c create mode 100644 drivers/clk/meson/c3-pll.h create mode 100644 include/dt-bindings/clock/amlogic,c3-peripherals-clkc.h create mode 100644 include/dt-bindings/clock/amlogic,c3-pll-clkc.h base-commit: 57b55c76aaf1ba50ecc6dcee5cd6843dc4d85239