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[80.71.142.18]) by smtp.gmail.com with ESMTPSA id t3-20020a1709064f0300b009b928eb8dd3sm5383396eju.163.2023.10.08.04.13.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Oct 2023 04:13:44 -0700 (PDT) From: =?utf-8?q?Alvin_=C5=A0ipraga?= To: =?unknown-8bit?q?Michael_Turquette_=3Cmturquette=40baylibre=2Ecom=3E=2C_?= =?unknown-8bit?q?Stephen_Boyd_=3Csboyd=40kernel=2Eorg=3E=2C_Rob_Herring_=3C?= =?unknown-8bit?q?robh+dt=40kernel=2Eorg=3E=2C_Krzysztof_Kozlowski_=3Ckrzysz?= =?unknown-8bit?q?tof=2Ekozlowski+dt=40linaro=2Eorg=3E=2C_Conor_Dooley_=3Cco?= =?unknown-8bit?q?nor+dt=40kernel=2Eorg=3E=2C_=A0ipraga__=3Calsi=40bang-oluf?= =?unknown-8bit?q?sen=2Edk=3E?= Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 0/3] clk: si5351: add option to adjust PLL without glitches Date: Sun, 8 Oct 2023 13:09:36 +0200 Message-ID: <20231008111324.582595-1-alvin@pqrs.dk> X-Mailer: git-send-email 2.42.0 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net From: Alvin Šipraga This series intends to address a problem I had when using the Si5351A as a runtime adjustable audio bit clock. The basic issue is that the driver in its current form unconditionally resets the PLL whenever adjusting its rate. But this reset causes an unwanted ~1.4 ms LOW signal glitch in the clock output. As a remedy, a new property is added to control the reset behaviour of the PLLs more precisely. In the process I also converted the bindings to YAML. Changes: v2 -> v3: - address further comments from Rob: - drop unnecessary refs and minItems - simplify if conditions for chip variants - ignore his comment about dropping '|', as line would be >80 columns - move additionalProperties: false close to type: object - define clocks/clock-names at top-level - drop patch to dove-cubox dts per Krzysztof's comment - will send separately - collect Sebastian's Acked-by v1 -> v2: - address Rob's comments on the two dt-bindings patches - new patch to correct the clock node names in the only upstream device tree using si5351 Alvin Šipraga (3): dt-bindings: clock: si5351: convert to yaml dt-bindings: clock: si5351: add PLL reset mode property clk: si5351: allow PLLs to be adjusted without reset .../bindings/clock/silabs,si5351.txt | 126 -------- .../bindings/clock/silabs,si5351.yaml | 268 ++++++++++++++++++ drivers/clk/clk-si5351.c | 47 ++- include/linux/platform_data/si5351.h | 2 + 4 files changed, 314 insertions(+), 129 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/silabs,si5351.txt create mode 100644 Documentation/devicetree/bindings/clock/silabs,si5351.yaml